Confined Channel FET Memory for Low Power Neuromorphic Computing
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Solution Overview
Problem
Current neural network implementations face challenges in efficiently storing and retrieving synaptic weights using conventional memory technologies, which are often power-intensive and not compatible with low-voltage CMOS logic, limiting their application in neuromorphic computing.
Innovation Solution
A memory cell utilizing a field effect transistor with a confined channel, where the stored value corresponds to the number of excess minority carriers, and is programmed by applying a selecting voltage and programming voltage within specific ranges to induce impact ionization without causing junction breakdown, allowing for low-power, multilevel storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If conventional memory technologies are used to store synaptic weights, then storage capability is provided, but power consumption increases and compatibility with low-voltage CMOS logic is lost
Solution Approach 1:
The patent changes the operating voltage parameter from conventional high voltages to low voltages (below 5V, preferably below 3V) by utilizing impact ionization effects that occur at these lower voltage levels. This enables the memory device to be compatible with standard low-voltage CMOS logic while maintaining storage functionality, thereby resolving the contradiction between power consumption and compatibility.
Solution Approach 2:
The patent replaces conventional memory mechanisms (such as charge storage in floating gates or conductance changes in resistive memory) with a field effect transistor-based mechanism that stores information through carrier concentration changes in the channel. This substitution enables direct integration with CMOS logic and operation at low voltages, eliminating the need for high-voltage conventional memory technologies.
2Productivity
If high programming voltage is applied to induce impact ionization, then storage value is changed, but junction breakdown may occur
Solution Approach 1:
The patent precisely controls the programming voltage parameter to remain below the breakdown voltage threshold while still achieving sufficient impact ionization for storage. By optimizing the voltage level and pulse width, the system achieves fast programming without causing harmful junction breakdown, resolving the contradiction between productivity and harmful effects.
Solution Approach 2:
The patent employs pulsed voltage application during programming, where the voltage is applied in controlled pulses rather than continuously. This periodic action allows impact ionization to occur during each pulse for efficient programming, while the intervals between pulses prevent thermal accumulation and junction breakdown, thus resolving the contradiction between programming speed and device safety.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient, low-power storage and retrieval of synaptic weights in neural networks, compatible with CMOS logic, facilitating the development of neuromorphic computing systems with reduced power consumption and increased scalability.
Implementation Method 1
programmed by applying a selecting voltage and programming voltage within specific ranges to induce impact ionization
Data Source
AI summary
A neuron circuit for use in a neural network is disclosed. The neural network includes a plurality of field effect transistors having confined channels. The sources and drains of the field effect transistors are connected in series. A plurality of input terminals for receiving a plurality of input voltages may be connected to a drain terminal of a corresponding field effect transistor. The threshold voltages of the field effect transistors can be programmed by increasing or decreasing a number of excess minority carriers in the confined channels, thereby programming the resistance presented by the field effect transistor.