Confined Lateral Switching Cell for ReRAM Scaling
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Solution Overview
Problem
Current resistive random access memory (ReRAM) stacks face challenges in scaling for three-dimensional structures due to limited area for metal deposition, leading to high resistance in vertical electrodes and inability to tune cell area independently from electrode dimensions, which affects switching characteristics and increases the risk of etch damage.
Innovation Solution
The implementation of a conformal metal-insulator-metal stack using atomic layer deposition (ALD) for a resistive switching memory stack, allowing for lateral switching and independent area modulation of the unit cell, decoupling cell footprint and metal oxide active area, and reducing the risk of etch damage through a confined cell scheme.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical stacking of ReRAM stacks is used to increase density, then storage density is improved, but the area for metal deposition is limited leading to high resistance in vertical electrodes
Solution Approach 1:
The patent transitions from conventional planar ReRAM structures to a three-dimensional vertical stacking architecture. Multiple ReRAM stacks are stacked vertically to increase storage density while maintaining reliable electrical connections through optimized vertical electrode design that extends through multiple stacking levels.
Solution Approach 2:
The patent implements a nested structure where vertical electrodes are positioned to pass through multiple ReRAM stack levels, with intermediate electrodes nested between stacking levels. This nested arrangement allows for extended current paths while maintaining compact footprint and reducing overall resistance through multiple parallel conduction paths.
2Ease of manufacture
If conventional ReRAM stack structure is used, then manufacturing is simplified, but cell area cannot be tuned independently from electrode dimensions affecting switching characteristics
Solution Approach 1:
The patent segments the ReRAM cell structure into distinct functional regions: active switching regions formed by metal oxide layers, inert electrode regions for current conduction, and intermediate regions for isolation. This segmentation allows independent optimization of cell footprint dimensions from active area dimensions, enabling flexible cell area tuning while maintaining manufacturing simplicity through standardized layer deposition processes.
Solution Approach 2:
The patent applies local quality by creating regions with different material properties and functions within the same device structure. Inert electrodes provide localized non-reactive contact regions, while metal oxide layers provide localized filament formation regions. This local differentiation enables independent control of electrical characteristics and geometric dimensions.
3Shape
If planarization or etch is performed for coplanar surface, then surface flatness is improved, but damage occurs to the metal oxide layer
Solution Approach 1:
The patent performs preliminary protective actions by forming inert electrodes and intermediate electrodes before planarization and etching processes. These electrode structures serve as protective masks and structural supports that prevent damage to the underlying metal oxide layers during subsequent surface treatment processes, ensuring both surface flatness and layer integrity.
Solution Approach 2:
The patent implements beforehand cushioning by depositing robust electrode materials and intermediate protective layers that cushion and protect the fragile metal oxide switching layers from mechanical stress and chemical damage during planarization and etching operations. This protective architecture ensures the metal oxide layers remain intact while achieving the required surface flatness for subsequent processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables low metal line resistances, optimized switching characteristics, increased current density, and deterministic filament formation, while minimizing edge effects and eliminating metal oxide etch damage, thereby improving the scalability and reliability of ReRAM cells in three-dimensional structures.
Implementation Method 1
The inert electrode is formed using atomic layer deposition (ALD). The metal oxide layer is formed using atomic layer deposition (ALD). The reactive electrode is formed using atomic layer deposition (ALD).
Data Source
AI summary
A memory device including a via opening through a dielectric layer and an inert electrode having a conformal thickness present on sidewalls but recessed from the top of the via and a base surface of the via opening through the dielectric layer. A metal oxide layer provides a filament forming layer for the memory device and is present in direct contact with the inert electrode. The metal oxide layer also has a conformal thickness and has vertically orientated portions on the portion of the inert electrode overlying the sidewalls of the via opening, and horizontally orientated portions on the portion of the inert electrode overlying the base of the via opening. A reactive electrode is in direct contact with the metal oxide layer. Switching of the memory device includes a laterally orientated direction across the vertically orientated portion of the metal oxide layer in regions not modified by patterning of the conformal metal-oxide layer.