Confined SiN Trap Layer Deposition for 3D-NAND Interference Control
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Solution Overview
Problem
Existing 3D-NAND memory stacks face performance degradation due to charge spreading and cell-to-cell interference, primarily caused by continuous charge trap layers, which hinder the scale-down of word line dimensions and lead to variations in trap layer shape and thickness.
Innovation Solution
A method for forming a confined trap layer by selective deposition using a sacrificial layer and deposition-enabling layer, where the trap layer is deposited only between the tunnel oxide and the word line, suppressing cell-to-cell interference and lateral charge spreading, and variations in trap layer shape and thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a continuous charge trap layer is formed by deposition, then the charge trap layer provides storage functionality, but charge spreading and cell-to-cell interference occur due to the continuous nature of the layer
Solution Approach 1:
The continuous charge trap layer is segmented into discrete confined charge trap regions by introducing voids between adjacent memory holes. This segmentation prevents charge spreading laterally between cells while maintaining vertical charge trapping functionality within each memory hole, thereby eliminating cell-to-cell interference caused by the continuous layer structure.
Solution Approach 2:
The harmful continuous portions of the charge trap layer are extracted by selectively removing material between memory holes to create voids. This extraction eliminates the charge spreading pathways that cause interference between adjacent cells, while preserving the essential charge trapping function within each confined region.
2Quantity of substance
If cell-to-cell distance is reduced to increase storage density, then more cells can be packed, but charge spreading and cell-to-cell interference are aggravated
Solution Approach 1:
By segmenting the charge trap layer into confined regions separated by voids, the patent enables reduced cell-to-cell distance without increasing interference. The voids act as isolation barriers that prevent charge spreading even when cells are densely packed, allowing higher storage density while maintaining signal integrity.
Solution Approach 2:
The voids between memory holes serve as intermediary isolation structures that prevent direct charge interaction between adjacent cells. This intermediary structure enables denser cell packing by providing physical and electrical separation, thereby increasing storage density without sacrificing reliability.
3Quantity of substance
If word line dimensions are scaled down to increase capacity, then storage capacity increases, but variations in trap layer shape and thickness occur
Solution Approach 1:
Segmenting the charge trap layer into confined regions within each memory hole provides independent formation zones that are less sensitive to dimensional variations. Each confined region can be precisely controlled during deposition, reducing the impact of scaling-induced variations on overall layer uniformity and improving manufacturing precision.
Solution Approach 2:
The confined charge trap structure allows local optimization of trap layer properties within each memory hole while maintaining scalability. The voids between holes provide natural boundaries that ensure uniform deposition conditions in each localized region, reducing shape and thickness variations even as overall device dimensions are scaled down.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses cell-to-cell interference and lateral charge spreading, allowing for improved performance and reliability of 3D-NAND memory devices by confining the trap layer and optimizing its deposition process.
Implementation Method 1
selectively depositing a trap layer in the second recessed region
Data Source
AI summary
Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.