Confined Via Seed Layer for Low Stress Electroplating
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Solution Overview
Problem
Existing methods for filling deep semiconductor vias, particularly through electroplating, face challenges due to high aspect ratios and large metal volumes, resulting in significant metal overburden and associated stress on wafers, which requires extensive chemical mechanical polishing (CMP) for removal.
Innovation Solution
A method involving a confined metal seed layer within the via, utilizing a mask with a conductive metal layer for electroplating, where the seed layer is limited to the via surfaces, minimizing overburden and stress by allowing electroplating only within the via, and using CMP or etching to remove external seed layer portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If electroplating is used to fill deep TSVs, then via fill speed and quality are improved, but metal overburden increases causing wafer stress
Solution Approach 1:
The patent applies local quality by making the seed layer conductive only at the via entrance region while maintaining insulation elsewhere. This is achieved through a multi-layer structure where a conductive material (first material) is deposited selectively at the via opening, and an insulating material (second material) is deposited over the remaining substrate surface. This localized conductivity enables electroplating current to flow only where needed, filling the via efficiently without creating overburden on surrounding areas, thus resolving the contradiction between fill speed and wafer stress.
2Manufacturing precision
If electroplating is used to fill deep TSVs, then via fill quality is improved, but CMP processing time increases
Solution Approach 1:
The patent uses local quality to confine the metal deposit to the via region by creating a localized conductive path only at the via entrance. The insulating material prevents current flow to surrounding areas, so metal is deposited exclusively within the via. This eliminates the need for extensive CMP to remove overburden, as there is no extraneous metal to remove, thus reducing CMP processing time while maintaining via fill quality.
Solution Approach 2:
The patent converts the potential harm of metal overburden into a benefit by using the insulating material to prevent overburden formation in the first place. The insulating layer, which might seem to add process complexity, actually prevents the creation of problematic overburden metal, thereby reducing subsequent CMP requirements and turning a potential disadvantage into a process simplification.
3Stress or pressure
If electroless plating is used to fill TSVs, then wafer stress is reduced, but via fill speed decreases
Solution Approach 1:
The patent merges the advantages of both electroless and electroplating methods. The process begins with electroless plating to establish an initial conductive layer and barrier, then transitions to electroplating by applying voltage through the localized conductive seed layer at the via entrance. This combination allows the process to benefit from the stress-reducing characteristics of electroless plating while achieving the high-speed fill capability of electroplating, thus resolving the contradiction between fill speed and stress reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves electroplated via fill with minimal overburden and reduced CMP processing, thereby minimizing stress on the wafer and simplifying the process with self-aligned masking and reduced patterning steps.
Implementation Method 1
utilizing a mask with a conductive metal layer for electroplating, where the seed layer is limited to the via surfaces, minimizing overburden and stress by allowing electroplating only within the via
Implementation Method 2
which requires extensive chemical mechanical polishing (CMP) for removal
Data Source
AI summary
A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.