Conformal EMI Shielding for Wafer-Level Semiconductor Packages
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Solution Overview
Problem
The increasing complexity and demand for miniaturization in electronic components pose challenges to the reliability and stability of wafer level packaging (WLP) technologies, particularly in protecting semiconductor components from external electromagnetic interference (EMI).
Innovation Solution
A semiconductor device with a conformal EMI shield is developed, where the shield is an outermost shell coupled to the ground terminal, using a conductive structure with both active and dummy portions to filter out external EMI and provide a discharging path, effectively reducing noise interference. The shield is designed to conformally cover the semiconductor package, ensuring proper function while maintaining a grounded path for noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wafer level packaging technology is used to achieve miniaturization, then the size of electronic components is reduced, but the reliability and stability against external EMI deteriorates
Solution Approach 1:
The patent implements a nested shield structure where an inner shield is placed inside the semiconductor package and an outer shield surrounds the package. The inner shield is coupled to the die pad while the outer shield is coupled to the package substrate, creating multiple nested layers of EMI protection that work together to block electromagnetic interference from different directions and sources.
Solution Approach 2:
The patent applies different shielding strategies to different regions of the semiconductor package. The inner shield is specifically positioned to protect the die and immediate surrounding area, while the outer shield provides broader protection for the entire package. This localized approach allows optimized EMI protection for each critical region without unnecessarily increasing overall package size.
2Reliability
If the shield is designed to conformally cover the outer surface of the semiconductor package, then the EMI protection is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent divides the EMI shielding function into separate segments: an inner shield and an outer shield that can be manufactured and positioned independently. This segmentation allows each shield to be fabricated using standard manufacturing processes and then assembled into the final package, reducing overall manufacturing complexity compared to creating a single complex conformal shield.
Solution Approach 2:
The patent transitions from attempting to create a single conformal three-dimensional shield to using multiple planar or simple geometric shields positioned at different dimensions and orientations. The inner shield is positioned within the package cavity while the outer shield surrounds the package, creating protection through spatial arrangement rather than complex surface conforming.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability and stability of semiconductor devices by effectively filtering out external EMI, ensuring proper function and reducing noise interference, thus addressing the challenges of miniaturization and complexity in WLP technologies.
Implementation Method 1
covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface. Moreover, the method further includes forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package
Data Source
AI summary
A method of manufacturing a semiconductor device includes providing a semiconductor die and surrounding a sidewall of the semiconductor die with a dielectric material. The method further includes forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die. The method further includes molding the semiconductor die and the PPI into an integrated semiconductor package. The method further includes covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface. Moreover, the method further includes forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.