Conformal FinFET Source/Drain Layers to Prevent Region Merging
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Solution Overview
Problem
The semiconductor industry faces challenges in forming source/drain structures for FinFETs that are conformal to the underlying semiconductor substrate, which can lead to unwanted damage and unsatisfactory size issues during the patterning process, affecting device performance and fabrication costs.
Innovation Solution
A method involving the formation of dummy gate structures, spacer layers, and in-situ processes in a furnace to create conformal silicon layers as source/drain regions, which includes removing native oxide layers, depositing and crystallizing silicon layers, and replacing dummy gates with metal gate structures, ensuring improved conformity and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional patterning processes are used to form source/drain structures, then fabrication complexity is reduced, but manufacturing precision deteriorates due to unwanted merged regions and size issues
Solution Approach 1:
The method performs preliminary actions by forming dummy gate structures and spacer layers before the actual source/drain region formation. The dummy gates are positioned to define the future source/drain regions, and spacer layers are deposited on the dummy gates to establish precise boundaries. This preliminary structuring enables subsequent etching and deposition processes to achieve conformal source/drain regions with accurate dimensions and spacing, preventing merged regions while maintaining fabrication manageability.
2Productivity
If simultaneous processing of multiple wafers is implemented, then productivity is improved, but manufacturing precision may deteriorate due to process control challenges
Solution Approach 1:
The furnace-based processing system is designed to simultaneously process multiple wafers in a universal manner. The dummy gate structures, spacer layers, and source/drain deposition processes are configured to work uniformly across all wafers in the furnace load. This multi-functional approach allows concurrent processing of 5-10 wafers through the same sequence of operations (oxide removal, silicon deposition, crystallization, doping), achieving high throughput while maintaining consistent conformality and threshold voltage control across all devices through standardized process parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents unwanted merged source/drain regions, enhances device performance by reducing contact resistance, and lowers fabrication costs through simultaneous processing of multiple wafers, while maintaining the integrity of the threshold voltage of FinFETs.
Implementation Method 1
removing native oxide layers
Implementation Method 2
depositing and crystallizing silicon layers
Implementation Method 3
crystallizing silicon layers
Data Source
AI summary
A semiconductor device includes a semiconductor fin, a gate structure, a doped semiconductor layer, and a dielectric structure. The semiconductor fin has a top portion and a lower portion extending from the top portion to a substrate. The gate structure extends across the semiconductor fin. The doped semiconductor layer interfaces the top portion of the semiconductor fin. In a cross-section taken along a lengthwise direction of the gate structure, the doped semiconductor layer has an outer profile conformal to a profile of the top portion of the semiconductor fin.