Conformal Gate Dielectric Structure for Low-Leakage HEMTs
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Solution Overview
Problem
Conventional high electron mobility transistors (HEMTs) face challenges in reducing gate current leakage and on-resistance (RON) while enhancing transconductance (gm) to meet industry requirements.
Innovation Solution
A semiconductor device structure comprising a substrate, semiconductor channel layer, semiconductor barrier layer, gate capping layer, dielectric layer, and gate electrode, where the dielectric layer conformally covers the gate capping layer and surrounds its periphery, and the gate electrode covers at least one sidewall of the gate capping layer, along with a method of fabrication that includes forming these layers to reduce current leakage and improve electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional HEMT structure is used, then device simplicity is maintained, but gate current leakage increases and electrical performance deteriorates
Solution Approach 1:
The gate structure is segmented into multiple components: gate electrode, gate capping layer, dielectric layer, semiconductor barrier layer, and semiconductor channel layer. This segmentation allows each layer to perform its specific function independently, reducing gate current leakage while maintaining overall device functionality.
Solution Approach 2:
The dielectric layer is introduced as a new dimensional element that conformally covers the gate capping layer and surrounds its periphery. This adds a protective dimension around the gate structure, effectively blocking current leakage paths without complicating the fundamental device operation.
2Reliability
If conventional HEMT structure is used, then manufacturing process is simple, but on-resistance is high and transconductance is low
Solution Approach 1:
The semiconductor barrier layer and semiconductor channel layer are formed with specific compositions and thicknesses before gate electrode deposition. This preliminary structuring optimizes the electrical performance (reducing on-resistance and increasing transconductance) before the final gate assembly, making the overall manufacturing process more efficient.
Solution Approach 2:
The patent optimizes specific parameters including the thickness of the semiconductor barrier layer (30-100 nm), the composition ratio of group III-V compounds, and the dielectric layer thickness (5-20 nm). These parameter changes improve electrical performance while using standard semiconductor fabrication techniques.
3Reliability
If gate electrode directly contacts gate capping layer, then device structure is simple, but gate current leakage increases
Solution Approach 1:
The dielectric layer acts as an intermediary between the gate electrode and the gate capping layer. It conformally covers the gate capping layer and provides electrical isolation, preventing direct contact and reducing gate current leakage while maintaining a manageable gate structure.
Solution Approach 2:
The dielectric layer is implemented as a thin film (5-20 nm) that conformally covers the gate capping layer. This thin film provides effective electrical isolation and protects against current leakage without adding significant structural complexity or volume to the gate assembly.
Data Source
AI summary
A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate capping layer, a dielectric layer, and a gate electrode. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate capping layer is disposed on the semiconductor barrier layer, and the dielectric layer conformally covers the gate capping layer and surrounds the periphery of the gate capping layer. The gate electrode is disposed on the dielectric layer and covers at least one sidewall of the gate capping layer.