Conformal Gate Dielectric Layers for Non-Planar Transistors
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Solution Overview
Problem
As semiconductor fabrication continues to reduce transistor structure sizes, providing effective electrical insulation between the gate structure and the channel region of non-planar transistors becomes increasingly challenging due to constrained dimensions, leading to difficulties in forming gate electrode structures without compromising insulation.
Innovation Solution
The implementation of multiple dielectric layers with varying dielectric constants, where a first layer extends conformally over the fin structure, a second layer with a higher dielectric constant is disposed between the first and a third layer, which extends under the gate structure and along the sidewall portions of spacer structures, promoting electrical insulation while minimizing errors in gate electrode fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single dielectric layer is used to provide electrical insulation in non-planar transistors, then the structure is simple to manufacture, but the electrical insulation effectiveness deteriorates as transistor dimensions scale down
Solution Approach 1:
The gate dielectric structure is segmented into multiple distinct layers: a first dielectric layer in contact with the channel region, a second dielectric layer with higher dielectric constant disposed over the first layer, and a third dielectric layer extending under the gate structure. This segmentation allows each layer to contribute differently to the overall insulation effectiveness, with the high-k second layer providing enhanced insulation where needed most.
Solution Approach 2:
The gate dielectric structure employs composite materials with different dielectric constants arranged in specific configurations. The combination of dielectric layers with varying properties (standard-k and high-k materials) creates a composite structure that achieves superior electrical insulation effectiveness compared to single-material layers, particularly in scaled-down transistor dimensions.
2Productivity
If the transistor structure size is reduced to improve integration density, then productivity increases, but the difficulty of providing effective electrical insulation worsens due to constrained dimensions
Solution Approach 1:
The gate dielectric structure applies local quality by positioning a high-dielectric-constant second layer specifically in the region where insulation is most critical - between the gate structure and the channel region. The first and third dielectric layers provide insulation in other critical regions. This localized optimization of dielectric properties ensures effective insulation throughout the scaled-down structure without requiring uniform complexity everywhere.
3Reliability
If multiple dielectric layers with varying dielectric constants are implemented, then electrical insulation effectiveness improves, but the device complexity increases
Solution Approach 1:
The solution adds a vertical dimensionality to the gate dielectric structure by stacking multiple dielectric layers with different dielectric constants at different vertical positions. The first layer contacts the channel, the second high-k layer is disposed over it, and the third layer extends under the gate structure. This vertical stratification of dielectric properties enhances insulation effectiveness without requiring lateral complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrical insulation of the channel region without sacrificing gate electrode formation, improving transistor performance by reducing channel region scattering and maintaining insulation effectiveness as transistor dimensions scale down.
Implementation Method 1
a first layer of a first dielectric material extends conformally over the fin structure
Implementation Method 2
a second layer of a second dielectric material extends conformally over an adjoining portion of the first layer, wherein the second dielectric material is of a dielectric constant which is greater than that of the first dielectric material
Implementation Method 3
a third layer of a third dielectric material extends under the gate structure and further extends conformally along adjoining sidewall portions of the spacer structures
Data Source
AI summary
Techniques and mechanisms to provide electrical insulation between a gate and a channel region of a non-planar circuit device. In an embodiment, the gate structure, and insulation spacers at opposite respective sides of the gate structure, each extend over a semiconductor fin structure. In a region between the insulation spacers, a first dielectric layer extends conformally over the fin, and a second dielectric layer adjoins and extends conformally over the first dielectric layer. A third dielectric layer, adjoining the second dielectric layer and the insulation spacers, extends under the gate structure. Of the first, second and third dielectric layers, the third dielectric layer is conformal to respective sidewalls of the insulation spacers. In another embodiment, the second dielectric layer is of dielectric constant which is greater than that of the first dielectric layer, and equal to or less than that of the third dielectric layer.