Conformal Interconnect Layout for Sub-18 Nm Pitch Patterning

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing patterning technologies face challenges in accurately and efficiently forming interconnect structures with sub-24 nm pitches and conformal features, leading to issues such as parasitic resistance, capacitance, and defects in semiconductor devices.

Innovation Solution

Employing self-aligned quadruple patterning (SAQP) with modular interconnect structures featuring orthogonal and conformal lines and jogs, formed through selective cuts after spacer deposition or dielectric fill, to create a serpentine layout with minimal steps and non-conformal features.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional lithographic patterning processes are used to fabricate interconnect structures, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at sub-24 nm pitch scales

Engineering Contradiction:
Improvepitch accuracyVSAvoidpatterning process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patterning process is divided into multiple discrete stages: forming mandrels at a relaxed pitch, depositing spacers, selectively removing portions, and repeating the process. This segmentation allows each stage to be optimized independently, achieving sub-24 nm precision through cumulative refinement rather than attempting single-step patterning.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Mandrels are formed in advance at a larger, more manufacturable pitch before the final fine-pitch features are created through spacer deposition. This preliminary structuring establishes a template that guides subsequent patterning steps, enabling precise positioning of sub-24 nm features without directly patterning them at full resolution.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If feature pitch is scaled down to sub-24 nm, then interconnect density is improved, but parasitic resistance and capacitance increase

Engineering Contradiction:
Improveinterconnect densityVSAvoidparasitic resistance and capacitance
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The patent introduces vertical dimensionality through multi-layer interconnect structures with conformal features that wrap around vias and junctions. This three-dimensional routing allows signals to bypass resistive paths and reduces capacitive coupling between adjacent lines by utilizing spatial separation in the vertical dimension rather than relying solely on horizontal spacing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent modifies geometric parameters of interconnect features including rounded corners, variable width sections, and optimized via dimensions. These parameter adjustments reduce electric field concentration at sharp corners (lowering capacitance) and optimize current distribution (reducing resistance), thereby mitigating parasitic effects while maintaining high density.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If conformal features are implemented in interconnect structures, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvefeature conformityVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Conformal spacers self-align to mandrel structures through deposition processes that automatically follow the mandrel contours. This self-aligning mechanism eliminates the need for additional alignment steps and complex positioning systems, achieving high precision conformal features through the inherent properties of the deposition process rather than through complex process control.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12417926B2Circuit interconnect structure
Publication Date: 2025.09.16 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US12417926B2 patent drawing
  • US12417926B2 patent drawing
  • US12417926B2 patent drawing

AI summary

One or more systems, devices and/or methods provided herein relate to a circuit device having a modular or selectively designed interconnect structure with a plurality of conformal features. In the semiconductor realm, such achievements can allow for fabrication of a device with sub 18 nanometer (nm) or lesser pitch between adjacent and/or parallel lines of the interconnect structure. A device can comprise a semiconductor device having an interconnect structure having a first set of parallel lines and a second set of parallel lines, where the lines of the first set can be arranged in a transverse direction to the lines of the second set. The lines of the first set can be disposed orthogonally to the lines of the second set. The first second sets of lines can comprise first and second rounded jogs that are conformal to one another and which connect the first set of lines to the second set of lines.