3DIC Package Structure with Conformal Protective Layer for TSV Reliability
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Solution Overview
Problem
The semiconductor industry faces challenges in the development of three-dimensional integrated circuits (3DICs) due to issues such as defects in the planarization process, which can lead to recesses and sharp morphologies on the surfaces of through-substrate vias (TSVs), affecting the reliability and yield of the 3DIC structure.
Innovation Solution
A method is introduced that involves forming a conformal layer over the die stack structure to cover recesses and defects, followed by a filling layer and a protective structure to prevent plasma etching arcing during the patterning of the metal circuit structure, and a planarization process to expose the top surfaces of TSVs, ensuring proper electrical connection and isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If a planarization process is performed on the top surface of the second die, then the surface is flattened to enable subsequent processing, but recesses and sharp morphologies are created on the TSV surfaces that can cause plasma etching arcing
Solution Approach 1:
A conformal layer is deposited over the planarized top surface of the second die before the metal circuit structure is formed. This preliminary action fills the recesses and covers the sharp morphologies on the TSV surfaces, preventing plasma etching arcing during subsequent patterning processes while maintaining the planarized surface geometry.
2Productivity
If the integration density is increased by stacking chips vertically to form 3DICs, then more components are integrated in a smaller area, but defects in the planarization process affect the yield and reliability of the structure
Solution Approach 1:
The conformal layer is deposited in advance over the die stack structure, particularly covering the TSV surfaces on the second die. This preliminary protective action prevents plasma etching arcing during subsequent metal circuit patterning, ensuring high yield and reliability of the 3DIC structure while maintaining the high integration density achieved through vertical stacking.
Data Source
AI summary
Provided is a semiconductor package structure including a first die having a first bonding structure thereon, a second die having a second bonding structure thereon, a metal circuit structure, and a first protective structure. The second die is bonded to the first die such that a first bonding dielectric layer of the first bonding structure contacts a second bonding dielectric layer of the second bonding structure. The metal circuit structure is disposed over a top surface of the second die. The first protective structure is disposed within the top surface of the second die, and sandwiched between the metal circuit structure and the second die.