Conformal Masking Layer for High-Density Micro-Via Routing
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Solution Overview
Problem
The increasing complexity and miniaturization of electronic devices pose challenges in packaging technology, including constrained routing density, high manufacturing costs, and complexity due to the need for additional redistribution layers and increased I/O per device, which complicates the fabrication of integrated circuit (IC) packages.
Innovation Solution
The use of an electronic package with a dielectric layer, a conformal masking layer, and a routing layer, where the conformal masking layer defines the size of micro-vias and is configured to form a conformal electrically conductive layer, allowing for high-density electrical connections and compatibility with conventional die bonding techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If circuit boards are reduced in size to accommodate space limitations, then device miniaturization is achieved, but routing density is constrained and limited below desired amounts
Solution Approach 1:
The patent transitions from planar routing to three-dimensional vertical routing by forming micro-vias through the dielectric layer. This allows electrical connections to extend in the vertical dimension, effectively increasing routing capacity without expanding the horizontal footprint of the device, thus resolving the contradiction between miniaturization and routing density.
Solution Approach 2:
The patent segments the routing function into multiple layers by creating stacked micro-vias and intermediate conductive layers. This segmentation allows independent optimization of each routing layer and enables complex signal paths to be distributed across multiple segments, thereby achieving high routing density in a compact volume.
2Adaptability or versatility
If additional redistribution layers are used to create desired double-sided I/O system, then I/O capability is improved, but the number of processing steps increases, further increasing cost and complexity
Solution Approach 1:
The patent merges the masking function and the via formation function into a single conformal masking layer structure. This layer simultaneously defines via locations, provides electrical connectivity, and serves as a planarization layer, thereby achieving double-sided I/O capability while reducing the number of separate processing steps and associated complexity.
Solution Approach 2:
The conformal masking layer is designed to perform multiple functions: it acts as a etch mask for via formation, provides electrical connectivity through embedded conductive material, and serves as an intermediate routing layer. This multi-functionality eliminates the need for separate redistribution layers, reducing manufacturing complexity while maintaining enhanced I/O capability.
3Adaptability or versatility
If increasing I/O per device is implemented to meet demand, then device functionality is improved, but routing density and number of vias required per device increases
Solution Approach 1:
The patent utilizes the vertical dimension by forming micro-vias that penetrate through the dielectric layer to create three-dimensional interconnects. This approach allows a high number of I/O connections to be packed into a compact horizontal area by stacking conductive paths vertically, thereby supporting increased I/O per device without proportionally increasing routing density in any single plane.
Data Source
AI summary
An electronic package and a method of making the same in provided. The electronic package includes a dielectric layer and a conformal masking layer disposed on at least a portion of the dielectric layer. The electronic package further includes a routing layer disposed on at least a portion of the masking layer and a micro-via disposed at least in part in the conformal masking layer and the routing layer. Further, at least a portion of the routing layer forms a conformal electrically conductive layer in at least a portion of the micro-via. Also, the conformal masking layer is configured to define a size of the micro-via. The electronic package further includes a semiconductor die operatively coupled to the micro-via.