Conformal Metal Cap for Semiconductor Die Charge Distribution

Solution Overview

Problem

The semiconductor industry faces challenges in miniaturization and packaging of semiconductor devices, particularly in stacked and bonded devices, where advanced bonding processes are needed to reduce physical size and improve integration density while addressing issues like charge distribution and thermal stress.

Innovation Solution

The solution involves bonding semiconductor dies to a substrate with a conductive protective cap to equalize charge distribution, using an encapsulant for protection, and forming through-substrate vias to enhance interconnectivity, along with a carrier attachment and thinning process to expose conductive layers for further bonding and redistribution layers for improved connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If semiconductor dies are stacked and bonded to reduce physical size, then integration density is improved, but charge distribution becomes uneven causing damage

Engineering Contradiction:
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

A conformal metal cap is deposited over each semiconductor die in the stacked structure. This metal cap acts as an intermediary conductive element that redistributes charge evenly across the surfaces of multiple bonded dies, preventing charge buildup damage while maintaining the high integration density achieved through stacking.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The conformal metal cap creates an equipotential surface over each die by providing a conductive path that equalizes charge distribution. This ensures that all points on the die surface are at the same electrical potential, preventing localized charge accumulation that could damage the semiconductor structures.

Inventive Principle:
Principle #12Equipotentiality

2Quantity of substance

If minimum feature size is reduced to increase integration density, then more components are integrated, but manufacturing precision becomes more difficult

Engineering Contradiction:
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The conformal metal cap extends the protective and charge-distributing function into the vertical dimension by coating the sidewalls and top surface of each die. This three-dimensional conformal deposition provides comprehensive coverage that enhances manufacturing robustness while maintaining small feature sizes in the planar dimensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If sophisticated bonding techniques are used to bond stacked devices, then integration density is improved, but device complexity increases

Engineering Contradiction:
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The conformal metal cap deposition process is performed before die bonding, merging the protective coating step with the bonding preparation. This integrated approach simplifies the overall manufacturing process by combining multiple functions (protection, charge distribution, and bonding interface preparation) into a single conformal deposition operation.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11488842B2Method of making semiconductor device package including conformal metal cap contacting each semiconductor die
Publication Date: 2022.11.01
  • US11488842B2 patent drawing
  • US11488842B2 patent drawing
  • US11488842B2 patent drawing

AI summary

A method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.