Conformal Spacer Etch Cycles for Uniform Nanosheet Profiles
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Solution Overview
Problem
Traditional plasma etch methods for semiconductor devices with advanced geometries, such as nanosheet and nanowire transistors, face issues with top versus bottom etch variations and isolated versus nested area etch variations, leading to poor epitaxial growth and device failure due to excess etching and spacer loss.
Innovation Solution
A method involving a substrate with a patterned structure and a conformally deposited spacer layer, where the surface is reacted with a plasma-excited etch gas containing fluorine, hydrogen, and nitrogen to form a reacted layer, which is then partially removed by ion bombardment, repeating the process to expose side surfaces while retaining the spacer layer in indentations, using a single plasma processing system at a controlled temperature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional plasma etch is used to remove spacer layer, then etching speed is improved, but etch profile uniformity deteriorates (top versus bottom etch variations and isolated versus nested area etch variations)
Solution Approach 1:
The continuous plasma etch process is segmented into multiple cyclic steps: (1) fluorine-based plasma reaction step to form ammonium fluorosilicate reacted layer, (2) ion bombardment removal step to remove the reacted layer, (3) nitrogen-based plasma stabilization step. Each cycle removes a controlled amount of spacer layer material while maintaining uniform etch profile across different areas.
Solution Approach 2:
The etch process uses periodic cyclic action with alternating plasma conditions. The process alternates between fluorine-containing plasma (for reacted layer formation) and ion bombardment conditions (for selective removal), repeating this cycle multiple times to achieve the desired etch depth while maintaining profile uniformity across isolated and nested areas.
2Reliability
If excessive etching is performed to expose side surfaces, then epitaxial growth quality is improved, but spacer layer thickness is reduced (leading to structural integrity issues)
Solution Approach 1:
The cyclic etch process provides feedback control through iterative removal. Each cycle removes a precise, controlled amount of spacer layer material, and the process can be repeated for a predetermined number of cycles or until a target thickness is reached. This feedback mechanism ensures that the side surfaces are adequately exposed for epitaxial growth while maintaining sufficient spacer layer thickness for structural integrity.
Solution Approach 2:
The process uses partial action by removing only the necessary amount of spacer layer material through controlled cyclic etching. Instead of excessive removal, the process carefully removes material in small increments (typically 1-5 nm per cycle) to achieve just enough exposure of side surfaces for high-quality epitaxial growth while preserving sufficient spacer thickness.
3Device complexity
If conventional etch methods are used, then process simplicity is maintained, but device reliability deteriorates (poor epitaxial growth and device failure)
Solution Approach 1:
The process changes plasma parameters by using different gas compositions in different steps: fluorine-containing gas (SF6, CF4, or NF3) during the reaction step to form ammonium fluorosilicate, and nitrogen-containing gas during the stabilization step. These parameter changes enable selective and controlled etching that improves device reliability while maintaining reasonable process complexity through automation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise, self-limited conformal etching, reducing etch profile issues and ensuring high-quality epitaxial growth by maintaining sufficient spacer thickness for structural integrity and isolation, thereby improving semiconductor device manufacturing.
Implementation Method 1
reacting a surface of the spacer layer with a plasma-excited first etch gas to form a reacted layer on the spacer layer
Implementation Method 2
removing at least part of the reacted layer by ion bombardment from exposure to a plasma-excited second etch gas
Data Source
AI summary
A method for forming a semiconductor device can include providing a substrate having a patterned structure comprising semiconductor materials, where the patterned structure has a side profile including indentations, such as a patterned film stack, and where a spacer layer is conformally deposited over the patterned structure and within the indentations, reacting a surface of the spacer layer with a plasma-excited first etch gas to form a reacted layer on the spacer layer, wherein the plasma-excited first etch gas includes fluorine, hydrogen, and nitrogen, and removing at least part of the reacted layer by ion bombardment from exposure to a plasma-excited second etch gas. The spacer layer can be SiOCN. The reacted layer can be ammonium fluorosilicate. The first etch gas can contain SF6, H2, and N2, or NF3, H2, and N2. The reacting and removing can be done at room temperature in a same chamber.