Conjoined-Core Processor Resource Sharing
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Solution Overview
Problem
The efficiency of transistor utilization in mainstream processor architectures decreases as the number of transistors on a die increases, leading to limited performance improvements, prompting the need for alternative multiprocessor architectures that effectively share resources between processors without incurring significant performance loss.
Innovation Solution
A conjoined-core processor system where first and second cores share a single floating point unit or a single memory interconnection network port, with dynamic and intelligent resource allocation based on topology, frequency of use, and contention avoidance, allowing for reduced area and power consumption while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single floating point unit or memory interconnection network port is shared between conjoined-cores, then area and power consumption are reduced, but resource contention and performance degradation may occur
Solution Approach 1:
The patent merges resource sharing between conjoined-cores by having first and second cores share a single floating point unit or memory interconnection network port. This consolidation reduces the total area and power consumption while maintaining acceptable performance through intelligent resource allocation.
Solution Approach 2:
The patent implements dynamic resource allocation where the shared floating point unit or memory port is dynamically assigned to different cores based on workload demands, contention levels, and performance requirements. This dynamic sharing optimizes resource utilization and minimizes performance degradation.
2Productivity
If more cores are placed on a single chip, then processing capacity increases, but transistor utilization efficiency decreases
Solution Approach 1:
The patent makes certain processor resources universal by designing them to be shared among multiple conjoined-cores. The floating point unit and memory interconnection network port serve multiple cores, increasing their utilization efficiency and enabling more cores to function effectively on a single chip.
Solution Approach 2:
By merging the floating point unit and memory port resources to serve multiple cores, the patent reduces redundant transistor usage and improves overall transistor utilization efficiency while maintaining high processing capacity through the increased core count.
3Loss of energy
If processor resources are shared between threads, then efficiency increases, but system complexity and scheduling difficulty increase
Solution Approach 1:
The patent segments the processor into conjoined-cores with clearly defined shared resources (floating point unit, memory port). This segmentation creates manageable sharing units with predictable access patterns, reducing the complexity of resource scheduling compared to fully shared architectures.
Data Source
AI summary
A processing system is provided for processing signals in a processor system including first and second conjoined-cores, and sharing a single floating point unit or a single memory interconnection network port by the first and second conjoined-cores.