Conjoined Memory Architecture for Low-Latency Overflow Storage
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Solution Overview
Problem
Processor-based systems face challenges with increased memory access latency and dynamic power consumption due to larger density memories, which are required for higher bandwidth but often incur unnecessary power consumption and inefficiencies during low-to-mid bandwidth traffic streams.
Innovation Solution
A conjoined memory system comprising a smaller and larger memory system, where incoming write requests are directed to the smaller system if available, and to the larger system if not, ensuring reduced access latency and power consumption while maintaining sufficient storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a larger density memory is used to handle peak bandwidth requirements, then storage capacity is improved, but memory access latency increases
Solution Approach 1:
The memory system is segmented into a first memory (smaller, faster) and a second memory (larger, slower). The first memory handles frequent access operations with low latency, while the second memory provides additional storage capacity for peak bandwidth requirements. This segmentation allows the system to achieve both low access latency for common operations and high storage capacity when needed.
2Quantity of substance
If a larger density memory is used to handle peak bandwidth requirements, then storage capacity is improved, but dynamic power consumption increases
Solution Approach 1:
The memory system is divided into a first memory with smaller storage capacity and lower power consumption, and a second memory with larger storage capacity but higher power consumption. By segmenting the memory system, the first memory can handle typical workloads with minimal power consumption, while the second memory remains in a lower power state until peak bandwidth requirements activate it.
Solution Approach 2:
The memory allocation is dynamic rather than static. The system can switch between using only the first memory for low-power operation and activating the second memory when peak bandwidth is required. This dynamic approach allows the system to adapt power consumption to actual workload demands, avoiding unnecessary power consumption during low-to-mid bandwidth traffic streams.
3Loss of time
If a smaller memory system is used to reduce access latency and power consumption, then access latency is improved, but storage capacity is reduced
Solution Approach 1:
The memory system is segmented into a first memory optimized for speed with smaller capacity, and a second memory providing additional storage capacity. This segmentation allows the system to maintain low access latency by keeping frequently accessed data in the first memory, while the second memory provides the necessary storage capacity for peak bandwidth requirements.
Solution Approach 2:
The conjoined memory system provides multi-functionality by combining two memory types with different characteristics. The system can operate in different modes: using only the first memory for low-power, low-latency operations, or activating the second memory when additional storage capacity is required. This universal design allows the same memory system to adapt to varying workload requirements.
Data Source
AI summary
Conjoined memory system that includes a larger memory system conjoined with a smaller memory system to support data storage in the larger memory system when the smaller memory system is unavailable, and related methods of performing memory accesses and computer-readable media are also disclosed. The conjoined memory system is configured to selectively direct new, incoming memory write requests for incoming data (e.g., incoming data packets to be stored) through a bypass data path to be written to memory entries in the smaller memory system if available for data storage (e.g., memory entry(ies) are free). Memory access latency and dynamic power expended for such memory accesses is reduced. However, if the smaller memory system is not available for data storage (e.g., memory entries are full), the conjoined memory system can selectively direct new, incoming memory write requests instead to the larger memory system to be stored in memory entries therein.