Connect Die Routing in Semiconductor Packages for Compact Reliability
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Solution Overview
Problem
Conventional semiconductor packages face issues of excess cost, decreased reliability, and large package sizes, which are not adequately addressed by existing technologies.
Innovation Solution
The development of a semiconductor package structure and method that includes a connect die for routing electrical signals between multiple semiconductor dies, utilizing interconnection structures such as copper pillars or conductive bumps, and a redistribution layer to enhance electrical connectivity and reduce package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor package structures are used, then manufacturing is simpler, but package size becomes too large and reliability decreases
Solution Approach 1:
The patent transitions from planar routing to three-dimensional vertical routing by stacking semiconductor dies and using through-silicon vias (TSVs) for inter-layer connectivity. This dimensional change enables compact package structures with high routing density, reducing overall package size while maintaining or improving reliability through shorter signal paths and better thermal management.
Solution Approach 2:
The patent implements nested interconnection structures where conductive bumps, redistribution layers, and TSVs are integrated within the semiconductor die stack itself. The connect die contains embedded interconnection structures that route signals between multiple functional dies, creating a compact nested architecture that reduces package size while enhancing reliability.
2Productivity
If conventional routing structures are used, then manufacturing is easier, but routing density is insufficient and costs increase
Solution Approach 1:
The patent divides the routing function into separate modular components: TSVs for vertical inter-layer connectivity, conductive bumps for die-to-die bonding, and redistribution layers for signal routing within dies. This segmentation enables independent optimization of each routing element and simplifies the manufacturing process by allowing standardized fabrication techniques for each component type.
Solution Approach 2:
The patent forms interconnection structures such as TSVs and conductive bumps during the semiconductor fabrication process before die assembly. This preliminary formation of routing structures enables subsequent die stacking and bonding operations to proceed more efficiently, increasing overall routing density while maintaining manufacturing ease through process integration.
Data Source
AI summary
A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die.