Connect Die Routing Electrical Signals Between Semiconductor Dies
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Solution Overview
Problem
Conventional semiconductor packages face issues of high cost, decreased reliability, and large package sizes, which hinder efficient manufacturing and performance.
Innovation Solution
A semiconductor package structure and method that includes a connect die for routing electrical signals between multiple semiconductor dies, utilizing advanced interconnection structures and manufacturing processes to enhance packaging efficiency and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packages are used, then manufacturing cost is reduced, but reliability decreases and package size increases
Solution Approach 1:
The patent transitions from planar 2D packaging to 3D vertical stacking by introducing through-silicon vias (TSVs) that penetrate the substrate vertically. This dimensional change allows multiple functional layers to be stacked above and below the substrate, increasing packaging density while reducing the lateral footprint of the package.
Solution Approach 2:
The patent implements a nested structure where conductive elements, insulation layers, and additional functional layers are sequentially deposited and stacked within the vertical space created by TSVs. Each layer is nested within the structure formed by previous layers, maximizing space utilization and reducing overall package size while maintaining reliability.
2Reliability
If conventional semiconductor packages are used, then manufacturing process is simplified, but cost increases and reliability decreases
Solution Approach 1:
The manufacturing process is segmented into distinct modular stages: substrate preparation with TSV formation, sequential deposition of conductive and insulating layers, intermediate annealing steps, and final encapsulation. Each stage can be independently optimized and controlled, making the complex process more manageable and manufacturable despite increased steps.
Solution Approach 2:
Through-silicon vias are formed and conductive plugs are deposited in preliminary steps before the main layer stacking process. This preliminary action prepares the vertical pathways and electrical connections in advance, enabling subsequent layers to be deposited more efficiently and reducing overall manufacturing complexity.
3Productivity
If advanced interconnection structures are implemented, then routing efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent employs universal TSV structures that serve multiple functions: mechanical support, electrical interconnection between layers, and thermal management pathways. This multi-functionality simplifies the overall design by using a single structural element for multiple purposes, reducing the need for separate specialized components and lowering manufacturing complexity.
Solution Approach 2:
The patent optimizes parameters such as TSV diameter, wall thickness, and material composition to balance routing efficiency with manufacturability. By carefully controlling these parameters within specific ranges, the design achieves high routing density while remaining compatible with existing semiconductor manufacturing capabilities.
Data Source
AI summary
A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die.