Connected Plane Stiffener for IC Chip Carrier Warpage Reduction
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Solution Overview
Problem
Coefficient of Thermal Expansion (CTE) mismatch between packaging materials leads to warpage and bow in electronic components, as materials with different CTEs expand and contract unevenly, causing mechanical stress and potential defects in electrical connections.
Innovation Solution
An integrated circuit (IC) chip carrier design featuring a plane region with an upper conductive plane separated from a lower conductive plane by a dielectric layer, connected via a conductive channel via, which resists bending moments and shear forces, thereby reducing warpage and bow by distributing power and ground potentials effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If materials with different CTEs are used in the carrier structure, then electrical connections and functionality are achieved, but warpage and bow occur due to thermal expansion mismatch
Solution Approach 1:
The patent changes the physical parameters of the carrier structure by introducing a stiffening layer with specific mechanical properties (higher modulus of elasticity) and optimizing its thickness and material composition to achieve the desired stiffness without significantly altering the CTE mismatch problem
Solution Approach 2:
The patent uses a composite structure combining the organic carrier material with a stiffening layer made of different materials (such as ceramic or metal) to achieve both electrical functionality and reduced warpage. The composite structure allows each layer to contribute its advantageous properties
2Stability of the object's composition
If the carrier structure is made stiffer to reduce warpage, then structural stability improves, but manufacturing complexity increases
Solution Approach 1:
The patent segments the carrier structure into distinct functional layers: the organic carrier base and a separate stiffening layer. This segmentation allows each layer to be optimized independently for its specific function while simplifying the overall manufacturing process through modular construction
Solution Approach 2:
The stiffening layer serves multiple functions simultaneously: it provides structural stiffness to reduce warpage, acts as a barrier layer, and can serve as an electrical reference plane. This multi-functionality reduces the need for additional separate components, thereby simplifying manufacturing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances the stiffness of the IC chip carrier, reducing warpage and bow, and improves the reliability of electrical connections by minimizing thermal expansion mismatches, leading to increased yield and efficient heat management.
Implementation Method 1
The upper conductive plane and the lower conductive plane resist bending moments internal to the IC chip carrier and the conductive channel via resists shear forces internal to the IC chip carrier
Implementation Method 2
The upper conductive plane and the lower conductive plane resist bending moments internal to the IC chip carrier
Data Source
AI summary
An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier.