Connected SAW Filter Layout for Tolerance-Stable Matching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Filter devices with multiple connected filter circuits are sensitive to production tolerances, leading to variations in parasitic elements and undesired changes in filter performance.
Innovation Solution
The filter device design places the common node on the surface of the substrate, with the first matching circuit realized on the multilayer panel, reducing the sensitivity to production tolerances and allowing for more precise setting of filter properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple filter circuits are integrated on a common chip, then cost is reduced and connection lines are shortened, but production tolerances cause wider spread of filter properties due to parasitic elements
Solution Approach 1:
The patent divides the filter device into two separate substrates: a first substrate containing the first filter circuit and a second substrate containing the signal path with the second filter circuit. This segmentation allows each filter circuit to be optimized and manufactured independently, reducing the impact of production tolerances on overall filter performance while maintaining the benefits of integration.
Solution Approach 2:
The patent introduces a bump connection structure as an intermediary element between the two substrates. This bump connection serves as a controlled interface that minimizes parasitic inductance and provides a stable mechanical and electrical connection, thereby reducing the sensitivity to production tolerances while enabling the integrated configuration.
2Device complexity
If filter circuits are connected via bump connections, then integration is achieved, but parasitic inductance varies with bump height causing undesired filter performance variation
Solution Approach 1:
The patent optimizes the geometric parameters of the bump connection structure, including its height, diameter, and material composition, to minimize parasitic inductance. By carefully controlling these parameters, the design reduces the sensitivity to manufacturing variations and achieves more stable filter performance across production batches.
Solution Approach 2:
The patent uses standardized bump connection designs that have been previously optimized and characterized. By replicating this proven connection structure across multiple devices, the variability introduced by production tolerances is minimized, as each bump connection behaves consistently with the established design parameters.
3Manufacturing precision
If common node is placed on substrate surface, then sensitivity to production tolerances is reduced, but wiring complexity on multilayer panel increases
Solution Approach 1:
The patent moves the common node from the substrate surface to the interior of the multilayer panel, utilizing the third dimension (depth) for wiring routing. This allows the common node to be electrically connected to both filter circuits through vertical vias and horizontal trace layers within the panel, reducing sensitivity to surface production tolerances while managing wiring complexity through structured multilayer design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces the impact of production tolerances on filter performance, stabilizing parasitic inductances and improving the precision of filter characteristics such as band edge position, insertion loss, and bandwidth.
Implementation Method 1
A piezoelectric substrate is mounted onto the top surface of the panel
Implementation Method 2
First and second filter circuit may be realized in SAW technique
Data Source
AI summary
A filter device having a reduced sensitivity to production tolerances comprises a multilayer panel with integrated wiring, a piezoelectric substrate mounted to the panel. A first filter circuit (FC1) and a signal path (SP) comprising a second filter circuit are realized on the substrate and connected to a common antenna terminal (AT) as well as to a common node (CN) located on top of the piezoelectric substrate. A first matching circuit (MC1) and further matching circuits (MC2) are realized by the wiring in the multilayer panel.


