3D Memory Connection Region Vertical Channels for Dense Stacking
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Solution Overview
Problem
Conventional two-dimensional semiconductor devices face limitations in integration density due to expensive process equipment and fineness of pattern formation, which hinders their ability to meet increasing consumer demands for higher performance and lower costs.
Innovation Solution
A three-dimensional semiconductor memory device is developed with vertically stacked electrodes and semiconductor patterns, including a substrate with cell and connection regions, and vertical structures that penetrate electrode structures, allowing for higher integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked structures. Multiple electrode structures and semiconductor patterns are stacked in the vertical direction (third direction perpendicular to substrate), enabling higher integration density without requiring finer lateral patterning. This dimensional change allows memory cells to be arranged in multiple layers, significantly increasing the quantity of storage elements per unit area.
2Quantity of substance
If pattern fineness is increased to improve integration, then integration density improves, but process equipment cost increases
Solution Approach 1:
Instead of increasing lateral pattern fineness to improve integration, the patent stacks multiple layers in the vertical direction. This approach achieves high integration density using coarser lateral patterning that is already available in existing manufacturing processes, thereby avoiding the need for expensive advanced lithography equipment while still achieving high integration.
Solution Approach 2:
The patent divides the memory structure into multiple discrete layers including first and second electrode structures, upper and lower semiconductor patterns, and insulating layers. Each layer can be formed using standard manufacturing processes, and the segmented modular structure allows for incremental fabrication without requiring single-step ultra-fine patterning, reducing equipment cost while maintaining high integration.
3Quantity of substance
If vertical structures are stacked to increase integration, then integration density improves, but device complexity increases
Solution Approach 1:
The complex three-dimensional structure is segmented into distinct functional layers: first electrode structure with first semiconductor pattern for memory cell formation, second electrode structure with second semiconductor pattern for connection region functionality, and insulating layers for electrical isolation. This segmentation allows each component to be formed and controlled independently, managing device complexity while achieving high integration through vertical stacking.
Solution Approach 2:
Different regions of the substrate are assigned different structures: the first region contains the first electrode structure and first semiconductor pattern for memory cell operations, while the second region contains the second electrode structure and second semiconductor pattern for connection functions. This local differentiation optimizes each region for its specific function, managing overall device complexity through specialized local designs.
Data Source
AI summary
A three-dimensional semiconductor memory device and a method of manufacturing the same. The device may include a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, a plurality of first vertical structures penetrating the electrode structures on the cell array region, and a plurality of second vertical structures penetrating the electrode structures on the connection region. Each of the first and second vertical structures may include a lower semiconductor pattern connected to the substrate and an upper semiconductor pattern connected to the lower semiconductor pattern.