Connective Exposure Alignment Marks for Semiconductor Pattern Accuracy
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Solution Overview
Problem
In connective exposure methods for semiconductor device manufacturing, achieving accurate and reproducible connection of adjacent patterns is challenging, leading to potential disconnections and hindrances in circuit refinement due to misalignment and superposition errors.
Innovation Solution
The method involves forming arrangement adjusting marks on a semiconductor substrate, either on X-dicing or Y-dicing regions, before exposing patterns, allowing for precise alignment and connection of patterns using these marks, thereby improving the accuracy and reproducibility of pattern connection during connective exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If connective exposure is performed by dividing a large pattern into multiple small patterns and exposing them sequentially, then large-sized semiconductor devices can be manufactured, but pattern connection accuracy deteriorates due to mask setting errors and stage movement errors
Solution Approach 1:
The patent introduces alignment marks as intermediary reference elements that are formed on the substrate before pattern exposure. These marks serve as mediators between different exposure fields, enabling accurate positioning and connection of patterns across multiple exposure steps by providing a common reference framework that compensates for mechanical positioning errors
Solution Approach 2:
The patent performs preliminary formation of alignment marks on the substrate before exposing the actual patterns. This preliminary action establishes a reference coordinate system that will be used throughout the connective exposure process, allowing subsequent patterns to be accurately positioned relative to previously exposed patterns despite stage movements and mask repositioning
2Reliability
If margins are added for pattern superposition to prevent disconnection upon alignment errors, then connection reliability improves, but circuit refinement is hindered due to increased pattern size
Solution Approach 1:
The patent replaces mechanical alignment methods (relying on physical mask positioning and stage movement accuracy) with an optical/reference-based alignment system using alignment marks. This substitution allows for precise pattern connection without requiring large mechanical margins, as the alignment marks provide a stable reference that enables accurate positioning at the sub-micron level, thus supporting circuit refinement while maintaining reliability
Data Source
AI summary
A method of manufacturing a semiconductor device answerable to refinement of circuits by correctly connecting adjacent small patterns with each other with excellent reproducibility in connective exposure and a semiconductor device manufactured by this method are proposed. According to this method of manufacturing a semiconductor device, connective exposure is performed by dividing a pattern formed on a semiconductor substrate into a plurality of patterns and exposing the plurality of divided patterns in a connective manner, by forming marks for adjusting arrangement of the patterns to be connected with each other on the semiconductor substrate before exposing patterns of a semiconductor element and connectively exposing the patterns of the semiconductor element in coincidence with the marks for adjusting arrangement.