Connectivity-Aware Layout Data Reduction for ESD Verification
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Solution Overview
Problem
Conventional ESD protection verification techniques face challenges with large netlist files, which can reach several GB in size, making them difficult to handle and slowing down processing times, despite the overwhelming number of circuit elements being irrelevant for evaluation.
Innovation Solution
The proposed solution involves a connectivity-aware reduction method that identifies circuit elements of interest, determines nets and cells of interest based on pins, and selects layout geometric elements for verification, preserving hierarchy and reducing data size without neglecting critical elements like ESD protection components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection verification techniques are used with full netlist files, then verification completeness is maintained, but processing time increases significantly and data handling becomes difficult
Solution Approach 1:
The patent extracts only the essential connectivity information (nets and cells of interest) from the complete netlist, filtering out irrelevant circuit elements. This extraction is performed by identifying pins of interest, determining connected nets and cells, and selecting only those layout geometric elements that correspond to the extracted connectivity data, thereby reducing verification data size while maintaining ESD protection evaluation accuracy
Solution Approach 2:
The verification process is segmented into distinct stages: identifying circuit elements of interest, determining nets and cells of interest, and selecting layout geometric elements. This segmentation allows the system to process only the necessary portions of the design at each stage, reducing overall processing time while maintaining verification completeness for critical ESD protection paths
2Measurement precision
If full layout data is used for verification, then verification accuracy is maintained, but data size becomes unmanageably large
Solution Approach 1:
The patent extracts only the essential connectivity information (nets and cells of interest) from the complete netlist, filtering out irrelevant circuit elements. This extraction is performed by identifying pins of interest, determining connected nets and cells, and selecting only those layout geometric elements that correspond to the extracted connectivity data, thereby reducing verification data size while maintaining ESD protection evaluation accuracy
Solution Approach 2:
The patent applies different levels of detail to different parts of the design. Critical ESD protection paths and their associated nets/cells are retained with full detail, while non-critical circuit elements are aggregated or omitted. This local quality approach maintains verification accuracy for critical areas while significantly reducing overall data size
Data Source
AI summary
Aspects of the disclosed technology relate to techniques of connectivity-aware reduction of layout data. With various implementations of the disclosed technology, circuit elements of interest are selected in a circuit design which includes netlist information and layout data. Based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, nets of interest are determined. Cells of interest, comprising cells that are identified based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, are then determined. Based on the nets of interest and the cells of interest, layout geometric elements are selected and may be analyzed for design verification. For electrostatic discharge (ESD) protection verification, the cells of interest may further comprise cells that include portions of power supply grids on top metal layers.