Connectivity Verification Partitioning for Electronic Design Efficiency
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Solution Overview
Problem
Conventional connectivity verification methods for electronic designs are inefficient due to the sheer amount of connectivity information, relying on brute force techniques that are computationally intensive and slow, especially as the complexity of modern electronic designs increases.
Innovation Solution
A method and system that partition connectivity information into multiple partitions, allowing for pre-proof verification using reverse connectivity and formal methods only when necessary, while blackboxing unnecessary modules and components to focus on essential connections, thereby reducing computational load and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If brute force techniques are used for connectivity verification, then verification completeness is improved, but computational time and resources increase significantly
Solution Approach 1:
The patent divides the connectivity verification problem into multiple partitions based on design hierarchy levels (e.g., top-level, module-level, sub-module-level). Each partition contains a subset of connections that can be verified independently. This segmentation allows the verification process to focus on specific regions rather than exhaustively checking all connections simultaneously, thereby reducing computational time while maintaining verification completeness through systematic coverage of all partitions.
Solution Approach 2:
The patent performs preliminary actions by identifying and blackboxing modules with known connectivity status before formal verification begins. Modules that have already been verified or have trivial connectivity are marked in advance and excluded from subsequent formal verification steps. This preliminary filtering reduces the scope of formal verification needed, decreasing computational resources and time while preserving verification thoroughness for remaining unverified connections.
2Measurement precision
If full elaboration is performed on the entire design, then verification accuracy is improved, but device complexity and resource requirements worsen
Solution Approach 1:
The patent applies local quality by performing full elaboration and formal verification only on specific partitions or regions of the design that require detailed verification, rather than uniformly elaborating the entire design. Different levels of elaboration are applied to different partitions based on their verification needs. This approach maintains high verification accuracy for critical regions while avoiding the device complexity and resource overhead of full-design elaboration.
Solution Approach 2:
The patent employs partial action by selectively elaborating only the necessary portions of the design required for verification of specific connection partitions, rather than performing excessive full elaboration on the entire design. The elaboration scope is adjusted to match the verification requirements of each partition, reducing device complexity and resource consumption while maintaining sufficient verification accuracy for the connections being verified.
3Reliability
If the number of connection checks increases with design complexity, then verification coverage is improved, but productivity and efficiency deteriorate
Solution Approach 1:
The patent segments the large set of connection checks into multiple smaller partitions organized by design hierarchy and functional modules. Each partition contains a manageable subset of connections that can be verified in parallel or sequentially with reduced computational overhead. This segmentation maintains comprehensive verification coverage across all connections while improving productivity by enabling efficient processing of divided connection sets through parallel verification of multiple partitions.
Solution Approach 2:
The patent introduces an intermediary blackboxing mechanism that acts as a mediator between the verification engine and complex modules. By blackboxing modules with known or trivial connectivity, the system reduces the number of detailed connection checks required while maintaining verification coverage. The blackboxing intermediary allows the verification process to skip unnecessary detailed checks, thereby improving verification efficiency without sacrificing coverage of critical connections.
Data Source
AI summary
Disclosed are techniques for verifying connectivity of an electronic design. These techniques Identify connectivity information for a design description of an electronic design, generate a partition of a plurality of partitions for the connectivity information by partitioning the connectivity into the plurality of partitions based in part or in whole upon one or more factors, and performing a pre-proof verification flow on the partition by proving or disproving at least one connection candidate of a plurality of connection candidates for the partition to generate proof results for the partition. These techniques may further additionally generate a property for a connection candidate that fails to result in definitive proof results and prove or disprove the property with formal methods or techniques.