Connector Board for Multi-Level IC Package Testing

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Solution Overview

Problem

Reliability testing of integrated circuit packages with stacked dice is challenging due to the need for different test apparatus for level 0, 1, and 2 interconnects, and existing methods fail to accurately replicate the end product environment, particularly in testing the IC dice and interposer reliability.

Innovation Solution

A circuit arrangement and method using a connector board and translator card to mount an IC package with level 0, 1, and 2 interconnects, allowing for in situ or ex situ testing of the package, enabling simultaneous testing of all interconnect levels and IC die functionality while mimicking the end product environment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate test apparatus are used for level 0, 1, and 2 interconnects, then each interconnect level can be tested with specialized equipment, but the testing process becomes complex and time-consuming with multiple setup changes

Engineering Contradiction:
Improveinterconnect reliabilityVSAvoidtesting apparatus complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple separate test apparatus into a single integrated test system. The connector board integrates test capabilities for level 0 (copper pillars), level 1 (solder bumps), and level 2 (ball grid array) interconnects into one unified platform, eliminating the need to switch between separate test equipment and reducing testing complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The connector board serves multiple functions simultaneously: it acts as a test platform for all interconnect levels, provides environmental chamber compatibility, enables both in-situ and ex-situ testing, and supports various IC package configurations. This multi-functional design replaces multiple specialized test apparatus with a single universal testing solution

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If the package is removed from the environmental chamber for testing, then component level testing can be performed with the test platform, but the testing does not replicate the level 2 interconnect connection to the printed circuit board in the end product

Engineering Contradiction:
Improveinterconnect failure detectionVSAvoidend product environment replication
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The connector board acts as an intermediary between the IC package and the test platform. It provides the missing level 2 interconnect connection that replicates the end product environment while simultaneously enabling test platform access. The connector board includes appropriate connectors that interface with the test platform, allowing precise measurement of interconnect failures while maintaining environmental chamber compatibility

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the BLR test board approach is used to test level 2 interconnects in an end product-like structure, then the reliability of level 2 interconnects can be tested, but the reliability of the IC dice and interposer cannot be tested

Engineering Contradiction:
Improvelevel 2 interconnect reliabilityVSAvoidcomprehensive testing capability
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The connector board is segmented into distinct functional regions that independently support testing of different interconnect levels. Level 0 test capabilities are provided through connections to the IC dice, level 1 through the interposer, and level 2 through the connector board's own test structures. This segmentation allows comprehensive testing of all components simultaneously without interference

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9341668B1Integrated circuit package testing
Publication Date: 2016.05.17 XILINX INC
  • US9341668B1 patent drawing
  • US9341668B1 patent drawing
  • US9341668B1 patent drawing

AI summary

A testable circuit arrangement includes an integrated circuit (IC) package. The IC package includes a package substrate, an interposer mounted directly on the package substrate with level 1 interconnects, and at least one IC die mounted directly on the interposer with level 0 interconnects. The package substrate of the IC package is mounted directly on a connector board with a soldered ball grid array of level 2 interconnects. The level 0, level 1, and level 2 interconnects include respective power, configuration, and test interconnects. Power, configuration, and test terminals of the connector board are coupled to the power, configuration, and test interconnects of the level 2 interconnects.