Connector Via Structures for Low-Resistance GAA Backside Interconnects

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Solution Overview

Problem

Integration of backside interconnect structures with gate-all-around (GAA) field effect transistors poses a challenge due to the need for etching patterned structures through device-level gate-all-around field effect transistors, leading to high electrical resistance and signal transmission delays.

Innovation Solution

The development of low resistance connection via structures that pass through device-level structures within semiconductor nanostructures, such as GAA field effect transistors, using anisotropic deposition and etching processes to form fin stack structures, hybrid dielectric fins, and gate template structures, followed by selective removal and epitaxial growth of source/drain regions to reduce electrical resistance and RC delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If etching patterned structures through device-level gate-all-around field effect transistors is used to integrate backside interconnect structures, then wiring density is improved, but electrical resistance increases and signal transmission delays occur

Engineering Contradiction:

Improvewiring densityVSAvoidelectrical resistance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The connector via structure is divided into multiple segments: a first portion extending through the backside interconnect structure and a second portion extending through the device-level GAA FET structure. This segmentation allows each portion to be optimized independently, with the first portion optimized for backside interconnect integration and the second portion optimized for low-resistance connection through the nanostructure, thereby reducing overall electrical resistance while maintaining high wiring density

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The connector via structure serves as an intermediary element that bridges the backside interconnect structure and the device-level GAA FET structure. This intermediate connector provides a low-resistance electrical path that mediates the connection between the two structures, eliminating the high resistance and signal delays that would result from direct etching through the GAA FET

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

Engineering Contradiction:

Improvewiring densityVSAvoidsignal transmission delays

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

By segmenting the connector via into distinct portions that can be formed through separate deposition and etching processes, the structure enables optimized signal transmission paths. The first portion through the backside interconnect and the second portion through the device-level structure allow for minimized RC delay in each region, reducing overall signal transmission delays while achieving high wiring density

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The connector via structure utilizes parameter changes in the form of different materials and geometries in different portions. The first portion may use materials and dimensions optimized for backside interconnect integration, while the second portion uses materials and dimensions optimized for low-capacitance, low-resistance connection through the GAA FET, thereby minimizing signal transmission delays

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed method reduces electrical resistance and voltage drop between GAA field effect transistors and backside metal interconnect structures, minimizing signal transmission delays and enhancing wiring density.

Implementation Method 1

using anisotropic deposition and etching processes to form fin stack structures

Methodology Applied

Scientific EffectAnisotropic deposition:

Implementation Method 2

followed by selective removal and epitaxial growth of source/drain regions

Methodology Applied

Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS20250275173A1Connector via structures for nanostructures and methods of forming the same

Publication Date: 2025.08.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.