Consolidated DRAM and Flash Memory Module with Controller
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Solution Overview
Problem
The throughput bottleneck in information processing devices, such as servers, arises from the difference in throughput between DRAM and PCI-SSD, leading to performance degradation due to the busy rate of the CPU memory bus when connecting high-speed DRAM and lower-speed flash memory to the CPU memory bus.
Innovation Solution
The implementation of a CPU memory bus configuration with a first memory module using DRAM and a second memory module with a different memory interface, controlled by a memory controller that allows data to be read from the flash memory and written to the DRAM within the same memory interface, reducing the number of memory bus paths required during sequential read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a memory module with both DRAM and flash memory is connected to the CPU memory bus, then data capacity is increased, but the busy rate of the CPU memory bus increases resulting in performance degradation
Solution Approach 1:
The memory system is segmented into two distinct modules: a first memory module with DRAM for high-speed access and a second memory module with flash memory for high-capacity storage. Each module has its own memory interface, allowing independent access paths that prevent the flash memory from blocking the DRAM bandwidth on the CPU memory bus.
Solution Approach 2:
A memory controller acts as an intermediary between the CPU memory bus and the memory modules. The controller manages data transmission by allowing the CPU to access DRAM through the memory bus while separately managing flash memory access, thereby preventing the flash memory's slower speed from congesting the memory bus.
2Quantity of substance
If flash memory is connected directly to the CPU memory bus, then storage capacity is increased, but read speed is limited by the slower flash memory interface
Solution Approach 1:
The DRAM module serves as an intermediary buffer between the flash memory and the CPU. Data is first read from flash memory to DRAM at the flash memory's slower speed, then quickly transferred from DRAM to the CPU through the high-speed memory bus interface, maximizing overall throughput.
Solution Approach 2:
The system performs preliminary data loading by transferring data from flash memory to DRAM before the CPU needs to access it. This pre-loading mechanism ensures that when the CPU issues read requests, the data is already available in the high-speed DRAM, reducing access latency.
Data Source
AI summary
In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory.