Constant-0 Flip-Flop Reconfiguration for IC Test Coverage
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Solution Overview
Problem
Random pattern resistant faults in integrated circuits (ICs) have lower detection probabilities, leading to reduced fault/test coverage, and the introduction of dedicated sequential flip-flops to address this issue significantly impacts the IC footprint.
Innovation Solution
Reconfiguring existing constant-0 flip-flops in integrated circuits to provide additional observable and controllable test points, allowing for improved fault detection without increasing the IC footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated sequential flip-flops are added to detect random pattern resistant faults, then fault detection capability is improved, but IC footprint increases significantly
Solution Approach 1:
The patent reconfigures existing constant-0 flip-flops to serve dual purposes: maintaining their original functional role while simultaneously providing test point capabilities for fault detection. This multi-functionality approach eliminates the need for dedicated test flip-flops, thereby improving fault detection capability without increasing IC footprint.
Solution Approach 2:
The patent changes the operational parameters of existing flip-flops by reconfiguring them through control signals (TDR, TCK, TDATA) to switch between functional mode and test mode. This parameter change enables the same hardware resources to provide both normal operation and enhanced fault detection, resolving the contradiction between reliability improvement and footprint expansion.
2Measurement precision
If additional test points are introduced to improve fault coverage, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent makes existing flip-flops universal by enabling them to function as both operational storage elements and test observation points. The same flip-flop infrastructure provides both normal circuit functionality and enhanced fault detection capabilities, improving measurement precision without adding complex dedicated test circuits.
Solution Approach 2:
The patent merges the test point functionality with the existing flip-flop structure by integrating test control logic (TDR, TCK signals) into the standard flip-flop operation. This combination eliminates the need for separate test circuits, thereby improving fault coverage while maintaining circuit simplicity.
Data Source
AI summary
An aspect relates to an integrated circuit (IC), including: a data path; a logic gate including a first input coupled to the data path, and a second input configured to receive a second input configured to receive a test data register (TDR) signal; and a first flip-flop including a data input coupled to an output of the logic gate. Another aspect relates to integrated circuit (IC), including: a first logic gate including a first input configured to receive a test data register (TDR) signal; a first flip-flop including a data input (D) coupled to an output of the first logic gate, and a data output (Q) coupled to a second input of the first logic gate; a first data path; and a second logic gate including a first input coupled to the data output of the first flip-flop and a second input coupled to the first data path.