Semiconductor Memory MAC Computing With Constant Bit-Line Current

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Solution Overview

Problem

Existing semiconductor devices struggle to efficiently perform a large number of Multiply-Accumulate (MAC) operations required by neural networks, particularly in applications like image recognition and autonomous vehicles.

Innovation Solution

A semiconductor memory device with a computation control circuit that manages a constant bit line current and an output circuit with a computation capacitor to perform MAC operations, utilizing a NAND flash memory structure to store and process data for efficient multiplication and accumulation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional semiconductor devices are used for neural network computations, then basic memory functions are provided, but efficient performance of large number of MAC operations is not achieved

Engineering Contradiction:
ImproveMAC operation throughputVSAvoidcomputation circuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory device is designed to perform both traditional memory functions and MAC operations using the same memory cell array and bit lines. The memory cells can operate in dual modes: storing data normally or performing multiplication operations where the stored data represents multiplicands and word line voltages represent multipliers, with charge transfer to bit lines representing products that are then accumulated.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The invention merges memory storage functionality with computation functionality into a single integrated structure. The bit lines serve dual purposes: as readout lines for memory operations and as accumulation lines for MAC operations. The computation control circuit integrates with the memory architecture to provide constant current sources for multiplication and accumulation operations without requiring separate dedicated computation hardware.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If dedicated computation circuits are added to perform MAC operations, then computational efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvecomputational efficiencyVSAvoidcircuit structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory device performs computation using its own existing structures without requiring external dedicated computation circuits. The memory cells themselves perform multiplication by controlling charge transfer based on stored data and applied voltages, and the bit lines perform accumulation by integrating charge from multiple memory cells. This self-service approach enables MAC operations while minimizing additional circuitry.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The invention replaces traditional electronic computation mechanisms (transistors performing logical operations) with a charge-based computation mechanism. Instead of using complex logic circuits to perform multiplication and accumulation, the system uses controlled charge transfer and capacitive coupling, where physical charge movement directly represents computational operations, simplifying the computational mechanism.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If bit line current varies during computation, then simple circuit control is maintained, but computation accuracy deteriorates

Engineering Contradiction:
Improvecomputation accuracyVSAvoidcurrent control circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The computation control circuit monitors and regulates bit line current to maintain it at a constant value during MAC operations. This feedback control ensures that the current used for charge transfer and accumulation remains stable, which is critical for accurate computation results. The constant current control compensates for variations that might occur due to process variations, temperature changes, or loading effects.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system maintains computation accuracy by controlling the bit line current parameter to remain constant throughout the computation process. Rather than allowing current to vary freely for simplicity, the invention deliberately maintains this parameter at a fixed value, which ensures that the relationship between stored data, applied voltages, and resulting charge transfer remains predictable and accurate for MAC operations.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The device efficiently performs MAC operations by controlling bit line currents and capacitor charges, enhancing the computational efficiency of neural networks.

Implementation Method 1

an output circuit including a first computation capacitor whose charge amount is changed according to the first bit line current during the computation operation

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

an amount of charge that flows between the first bit line and the source line during the computation operation depends on both data store in a memory cell among the plurality of memory cells according to a first data and a voltage of a word line connected to the memory cell provided according to a second data

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS12444467B2Semiconductor memory device performing a multiplication and accumulation operation
Publication Date: 2025.10.14 SK HYNIX INC
  • US12444467B2 patent drawing
  • US12444467B2 patent drawing
  • US12444467B2 patent drawing

AI summary

A semiconductor memory device includes a cell array including a plurality of memory cells connected between a first bit line and a source line; a computation control circuit configured to control a first bit line current between the first bit line and the source line during a computation operation; and an output circuit including a first computation capacitor whose charge amount is changed according to the first bit line current during the computation operation, wherein an amount of charge that flows between the first bit line and the source line during the computation operation depends on both data stored in a memory cell among the plurality of memory cells according to a first data and a voltage of a word line connected to the memory cell provided according to a second data.