Constant Division Circuitry Using Carry-Save Modulo Reduction
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Solution Overview
Problem
Current methods for performing division by a constant in graphics processors are inefficient, particularly due to the growth of lookup tables with increasing divisors, redundancy in multiplication arrays, and failure to return a quotient when the remainder is non-zero.
Innovation Solution
The implementation of circuitry that performs constant division and modulo operations using carry-save modulo reduction, optimizing the processing of division and modulo operations within graphics processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If lookup tables are used for constant division, then division operation can be performed, but the lookup tables grow exceptionally as the divisor increases
Solution Approach 1:
The patent segments the division operation into multiple smaller steps using a tree structure of lookup tables. Instead of using a single large lookup table, the division is broken down into a series of smaller lookup tables organized in a binary tree structure, where each node performs a partial division and the results are combined to achieve the final quotient.
Solution Approach 2:
The patent transitions from a one-dimensional linear lookup table to a two-dimensional tree structure. The lookup tables are organized hierarchically in levels, with each level performing a portion of the division operation. This dimensional change allows the system to handle larger divisors without proportionally increasing the total storage requirements.
2Productivity
If multiplying by the reciprocal is used for division, then division can be performed, but multiplication arrays have repeated entries producing redundant gates
Solution Approach 1:
The patent extracts only the necessary multiplication operations from a full multiplication array. Instead of implementing a complete multiplication table with all possible combinations (including repeated entries), the method identifies and implements only the unique multiplication operations required for the specific constant divisor, eliminating redundant gates.
Solution Approach 2:
The patent changes the approach from general multiplication to optimized multiplication by the reciprocal. Instead of using a full multiplication array, the system calculates the reciprocal of the divisor and performs multiplication operations that are tailored to the specific constant, reducing the number of required gates while maintaining accuracy.
3Productivity
If shift adds are used for specific divisor values, then division can be performed, but the quotient is not returned when the remainder is non-zero
Solution Approach 1:
The patent creates a universal division method that works for all divisor values, not just specific ones. The tree structure of lookup tables and the multiplication by reciprocal approach can handle any constant divisor, unlike shift-add methods that are limited to specific values. This universal approach ensures the quotient is correctly returned regardless of the remainder.
Solution Approach 2:
The patent incorporates feedback mechanisms to verify and correct the division results. The system checks whether the calculated quotient and remainder are correct by multiplying the quotient by the divisor and adding the remainder, then comparing this result to the original dividend. If there is an error, the system adjusts the quotient accordingly, ensuring accurate results for all cases including when the remainder is non-zero.
Data Source
AI summary
The techniques described in the detailed description above enable the manufacturing of circuits with increased performance and efficiency when performing division by a constant number. One embodiment provides circuitry including an input circuit to receive an input value including a plurality of bits, a logarithmic tree coupled with the input circuit, the logarithmic tree configured to compute an array of values based on a plurality of multi-bit groups of the plurality of bits of the input value, each value in the array of values includes a modulus of a corresponding multi-bit group with respect to the constant, a binary array adder to compute a quotient of the division operation based on the array of values, the input value, and the constant, and an output circuit to output the quotient.