Constant-gm Bias Circuit With Drain-Voltage Feedback Control
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Solution Overview
Problem
Conventional constant gm bias circuits are unsuited for deep submicron CMOS technologies as they fail to accurately stabilize transconductance due to the influence of drain-source voltage, leading to design challenges in high-speed, high-density silicon ICs.
Innovation Solution
A constant transconductance bias circuit with a linear transconductance core circuit and a current mirror, utilizing negative feedback loops and a reference voltage to control drain bias, ensuring stable transconductance and identical bias settings between the bias circuit and application circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional constant gm bias circuits are used in deep submicron CMOS technologies, then the circuit structure is simple, but the transconductance stabilization is inaccurate due to drain-source voltage influence
Solution Approach 1:
The patent implements a feedback mechanism where the drain-source voltage of the first transistor is fed back to control the gate voltage of the second transistor through a control circuit. This feedback loop compensates for drain-source voltage variations, ensuring accurate transconductance stabilization despite the complexity introduced by the additional control path.
Solution Approach 2:
The patent dynamically adjusts the gate voltage of the second transistor based on the drain-source voltage of the first transistor. By changing the control parameter (gate voltage) in response to voltage variations, the circuit maintains constant transconductance across different operating conditions in deep submicron technologies.
2Stability of the object's composition
If drain-source voltage control is implemented to stabilize transconductance, then transconductance stability is improved, but the circuit complexity increases
Solution Approach 1:
The control circuit establishes a feedback relationship where drain-source voltage information is used to adjust the gate voltage of the second transistor. This feedback mechanism automatically maintains transconductance stability without requiring complex external control systems, as the circuit self-regulates based on its own operating parameters.
Solution Approach 2:
The bias circuit uses its own drain-source voltage as the control signal source, making the system self-regulating. The control circuit processes the internal voltage information to automatically adjust transistor operating points, eliminating the need for external control mechanisms and reducing overall system complexity while maintaining stability.
3Measurement precision
If negative feedback loops with differential amplifiers are used to control drain bias, then bias accuracy is improved, but the number of components increases
Solution Approach 1:
The patent combines the functions of drain bias control and transconductance stabilization into a single integrated control mechanism. The negative feedback loop simultaneously achieves both objectives by using the same control path to regulate drain voltage and maintain constant transconductance, thereby reducing the need for separate control circuits and minimizing component count.
Solution Approach 2:
The control circuit performs multiple functions: it amplifies the differential voltage signal, generates the appropriate gate voltage adjustment, and maintains drain bias accuracy all through a single integrated path. This multi-functional approach eliminates the need for separate dedicated circuits for each function, reducing the overall number of components while achieving high precision.
Data Source
AI summary
A bias circuit includes a linear core circuit CC with first and second mutually type corresponding transistors (M1; M2) and a current mirror CM with third and fourth transistors (M3; M4) of opposite type of M1 and M2. To obtain an equilibrium with a constant transconductance of the first transistor, first and second negative feedback loops (L1; L2) are applied, one including the linear core circuit CC, the other including the current mirror CM. In a first setting one loop suppresses differences between first and second drain voltages (Vd1; Vd2) and the other loop suppresses differences between one of of the first and second drain voltage Vd1 and Vd2 and a reference voltage Vref. In the second setting, one loop suppresses differences between the first drain voltage Vd1 and the reference voltage Vref and the other loop differences between the second drain voltage Vd2 and the reference voltage Vref.