Constant Modulo Recirculant Reduction Circuit
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Solution Overview
Problem
Current methods for performing constant modulo operations in graphics processors are inefficient, particularly when dealing with large divisors, as they result in redundant gates and do not provide a quotient when a remainder is expected, and existing solutions such as lookup tables and shift add methods have limitations.
Innovation Solution
The implementation of an optimal reduction scheme for reducing an array of bits modulo a constant using binary operations, which generates an optimal circuit for performing modulo operations based on odd integer constants, avoiding redundant gates and ensuring accurate quotient calculation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If lookup tables are used for constant modulo operations, then the operation can be performed, but the hardware complexity grows exceptionally as the divisor increases due to redundant gates
Solution Approach 1:
The patent segments the constant modulo operation into multiple phases: computing partial remainders for each bit of the input, accumulating these partial remainders, and producing the final result. This segmentation allows the use of simple, reusable circuit elements (adders and multiplexers) rather than a monolithic lookup table, reducing hardware complexity while maintaining operational capability.
Solution Approach 2:
The patent transforms the traditional approach from a spatial lookup table into a temporal iterative process with multiple phases. By adding a time dimension through sequential computation steps, the solution avoids the exponential growth of hardware complexity associated with large lookup tables while achieving the same modulo operation functionality.
2Productivity
If shift add approach is used for constant modulo operations, then the operation can be performed, but the quotient is not returned when the remainder is expected to be non-zero
Solution Approach 1:
The patent employs a dynamic iterative algorithm that adapts its computation based on the input value and divisor. The algorithm dynamically determines the quotient through the recirculant reduction process, where the quotient bits are generated sequentially as the remainder is computed, ensuring both the quotient and remainder are accurately produced even when the remainder is non-zero.
3Productivity
If multiplying by the reciprocal is used for constant modulo operations, then division can be performed, but multiplication arrays have repeated entries producing gate level netlists with redundant gates
Solution Approach 1:
The patent extracts and eliminates the redundant multiplication step by directly implementing the recirculant reduction algorithm using addition and bit-shifting operations. By taking out the multiplication operation entirely and replacing it with simpler arithmetic operations, the solution avoids the repeated entries and redundant gates inherent in multiplication arrays while maintaining the ability to perform division-like operations.
Data Source
AI summary
Described herein is a generalized optimal reduction scheme for reducing an array modulo a constant. The constant modulo operation calculates a result for array of bits xi, width n modulo an odd positive integer constant d, (e.g., x[n:0] mod d). Circuitry to perform such operation can be configured to compress the array of bits xi, width n into an array of bits yi width m. The techniques described herein enable the design of optimal circuitry via iterative exploration of all potential reduction strategies that are available given the input constraints.