Laterally Constrained Phase Change Memory Pillar for Low Reset Current
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Solution Overview
Problem
Prior art phase change memory (PCM) devices require high reset current and suffer from proximity thermal disturb issues due to inadequate current density and thermal management between memory cells during reset operations.
Innovation Solution
The PCM device incorporates laterally constricted structural elements with recessed sidewalls, enhancing current density at the interface with the phase change material, and includes air gaps to confine thermal energy, reducing heat transfer and program disturb effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional PCM device structure is used, then device simplicity is maintained, but reset current is high and thermal management is inadequate
Solution Approach 1:
The patent applies local quality by creating laterally constricted structural elements with varying cross-sectional areas at different locations within the memory pillar. Specifically, the memory element has a first cross-sectional area at its interface with the selector element and a second cross-sectional area at its interface with the phase change material, where these areas are deliberately different to optimize current density distribution and reduce reset current requirements while maintaining device functionality
Solution Approach 2:
The patent transitions from conventional two-dimensional planar structures to three-dimensional vertically stacked structures with laterally constricted elements. This dimensional change enables complex current pathways and thermal management characteristics that cannot be achieved in planar configurations, allowing for reduced reset current through optimized current density distribution in the vertical dimension
2Object-affected harmful factors
If conventional PCM device structure is used, then manufacturing process is simple, but thermal energy confinement is inadequate causing program disturb
Solution Approach 1:
The patent applies segmentation by dividing the memory pillar into distinct functional segments with different geometric characteristics. The laterally constricted structural elements create segmented regions that confine thermal energy to specific zones, preventing thermal propagation to adjacent cells while maintaining manufacturability through standardized fabrication processes
Solution Approach 2:
The patent utilizes parameter changes by varying the cross-sectional area parameters of the memory element at different vertical positions. This geometric parameter variation creates regions of different thermal mass and heat conduction characteristics, enabling thermal energy confinement that reduces program disturb effects while being compatible with existing manufacturing capabilities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for lower reset voltage and current usage, effectively reducing operational power and minimizing thermal interference between adjacent memory cells, thereby improving reset efficiency and stability.
Implementation Method 1
enhancing current density at the interface with the phase change material
Implementation Method 2
includes air gaps to confine thermal energy, reducing heat transfer and program disturb effects
Data Source
AI summary
A phase change memory device includes first conductive rails laterally extending along a first horizontal direction over a substrate, a rectangular array of memory pillar structures overlying top surfaces of the first conductive rails, and second conductive rails laterally extending along a second horizontal direction and overlying top surfaces of the rectangular array of memory pillar structures. Each memory pillar structure includes a vertical stack of structural elements including, from one end to another, a selector-side conductive element, a selector element, a selector-memory conductive element, a phase change memory element, and a memory-side conductive element. At least one structural element within the vertical stack is a laterally constricted structural element having laterally recessed sidewalls relative to sidewalls of a respective immediately vertically underlying structural element.


