Constraint-Driven Electronic Design Implementation
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Solution Overview
Problem
Recent advances in semiconductor design and fabrication, particularly in very deep submicron methodologies, introduce complexities in physical implementation tools for integrated circuits, making it challenging to adhere to newly devised constraints while meeting performance goals, especially in supporting design rule compliance during the placement and routing processes.
Innovation Solution
The implementation of constraint-driven techniques that involve data checking and preparation based on design rules, allowing for structured physical implementation strategies that automatically satisfy design rules, thereby reducing the burden on physical implementation tools and improving runtime efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physical implementation tools are used to adhere to design rules in very deep submicron methodologies, then design rule compliance is achieved, but tool complexity and runtime increase
Solution Approach 1:
The patent applies preliminary action by performing data checking and preparation based on design rules before the actual physical implementation process. This pre-processing step identifies and flags potential design rule violations in advance, allowing the physical implementation tools to work with pre-validated data, thereby reducing tool complexity and runtime while maintaining design rule compliance
2Reliability
If physical implementation tools are used to adhere to design rules in very deep submicron methodologies, then design rule compliance is achieved, but runtime efficiency decreases
Solution Approach 1:
The patent performs data checking and preparation based on design rules before physical implementation, identifying potential violations in advance. This preliminary validation reduces the runtime burden on physical implementation tools by pre-processing the data, thereby improving runtime efficiency while maintaining design rule compliance
Solution Approach 2:
The patent introduces an intermediary data checking and preparation step that acts as a mediator between the design input and physical implementation tools. This intermediary process validates data against design rules before they reach the physical implementation tools, reducing their computational burden and improving overall runtime efficiency
3Manufacturing precision
If manual verification and optimization of integrated circuit layout is performed, then design accuracy is improved, but time consumption increases
Solution Approach 1:
The patent implements self-service by automating the data checking and validation process against design rules. The system performs automatic verification of layout data without requiring manual intervention, thereby maintaining high verification accuracy while significantly reducing time consumption compared to manual methods
Data Source
AI summary
One aspect checks and prepares design data (202) based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation (204) is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s), without performing additional design rule checking on the design rule(s). Additional physical implementation (206) may be optionally performed for portion(s) of the electronic design not implemented with the structured physical implementation. Layout fixing or optimization may be optionally performed to fix design rule violations in the additional physical implementation results, if any, or to optimize the additional physical implementation results.