Circuit Constraint Set Comparison Using Endpoint Tag Propagation

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Solution Overview

Problem

Comparing different versions of circuit design constraints is computationally expensive and inefficient, particularly when dealing with path-related constraints, due to the exponential nature of existing path tracing methods, leading to excessive resource consumption.

Innovation Solution

A method that uses phase-based checks at timing endpoints to determine equivalent and non-equivalent path exceptions by embedding tags in timing data during propagation, allowing for linear-time comparison of constraint sets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If path tracing methods are used to compare constraint sets, then comparison accuracy is improved, but computational complexity increases exponentially

Engineering Contradiction:
Improvecomparison accuracyVSAvoidcomputational complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the constraint comparison problem into two independent parts: (1) comparing timing endpoints to identify mismatches, and (2) separately analyzing path exceptions. This segmentation avoids the exponential complexity of traditional path tracing while maintaining comparison accuracy through endpoint-based validation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces timing endpoints as intermediary objects that mediate between constraint sets and path exceptions. By comparing endpoints first and then selectively analyzing path exceptions only where needed, the method reduces computational complexity while preserving measurement precision.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If traditional path tracing is used for constraint comparison, then comprehensive constraint verification is achieved, but runtime consumption increases

Engineering Contradiction:
Improveconstraint verificationVSAvoidruntime consumption
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary comparison of timing endpoints before conducting detailed path exception analysis. This preliminary action identifies mismatch locations in advance, allowing the system to focus computational resources only on relevant path exceptions, thereby reducing overall runtime while maintaining comprehensive verification.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Instead of tracing all paths comprehensively, the patent applies partial action by analyzing path exceptions only at endpoints where mismatches are detected. This selective approach reduces runtime consumption while maintaining sufficient constraint verification through targeted analysis.

Inventive Principle:
Principle #16Partial or excessive action

3Measurement precision

If exhaustive path tracing is performed, then all constraint exceptions are detected, but computing resources are consumed excessively

Engineering Contradiction:
Improveexception detectionVSAvoidcomputing resources
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent extracts and compares timing endpoints separately from path exceptions. By taking out endpoint comparison as an independent step, the method detects exception locations without requiring exhaustive path tracing, thereby reducing computing resource consumption while maintaining exception detection precision.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The timing endpoints serve themselves by providing location information that guides subsequent path exception analysis. This self-service mechanism allows the system to detect exceptions efficiently without requiring external comprehensive path tracing, reducing computing resource usage.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12475286B1System and method for comparing circuit design constraint sets
Publication Date: 2025.11.18 CADENCE DESIGN SYST INC
  • US12475286B1 patent drawing
  • US12475286B1 patent drawing
  • US12475286B1 patent drawing

AI summary

Embodiments included herein are directed towards a method for comparing constraint sets. The embodiments may include determining, using at least one processor, at least one arrival propagation time corresponding to at least one endpoint, the at least one endpoint associated with a first constraint set and a second constraint set. The embodiments may further include creating, using the at least one processor, a first tag associated with the first constraint set and a second tag associated with the second constraint set. The embodiments may also include determining, using the at least one processor, at least one of: a non-equivalent path exception corresponding to the at least one endpoint and based at least in part on at least one of the arrival propagation time, the first tag, and the second tag; and an equivalent path exception corresponding to the at least one endpoint.