Constraint-Based Equivalence Checking for Digital Circuit Trace Containment
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Solution Overview
Problem
Current digital circuitry design verification methods require significant computational resources due to exponential resource usage with respect to design size, making it challenging to reduce design size and identify design flaws efficiently.
Innovation Solution
The implementation of constraint-based uncorrelated equivalence checking to identify trace-containment in sequential circuitry designs by obtaining candidate input sets, uncorrelating them, checking equivalence, and imposing constraints to avoid mismatches, thereby simplifying the design netlist and reducing computational burden.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verification algorithms are applied to digital circuitry designs, then design flaws can be detected, but computational resources increase exponentially with design size
Solution Approach 1:
The verification process is divided into multiple passes, with each pass focusing on specific design portions or aspects. The algorithm segments the computational task by iteratively refining equivalence checks on subsets of the design, allowing verification of large designs without requiring exponential resources for the entire design at once.
Solution Approach 2:
The method performs preliminary equivalence checking using simplified models or abstracted representations of the design before conducting full verification. By establishing trace-containment relationships in advance through constraint-based uncorrelated equivalence checking, the algorithm reduces the computational burden of subsequent detailed verification steps.
2Productivity
If the design netlist is simplified to reduce size, then verification becomes more efficient, but design accuracy may be compromised
Solution Approach 1:
The verification system dynamically adjusts the level of abstraction and simplification applied to the design netlist based on the verification stage and requirements. The algorithm transitions between different levels of design representation, applying simplifications only where and when they do not compromise the ability to detect design flaws, thus maintaining accuracy while improving efficiency.
Solution Approach 2:
The method changes parameters of the verification process, such as the depth of equivalence checking, the level of abstraction, and the constraints applied to input sets. By adjusting these parameters iteratively, the system achieves verification efficiency without sacrificing design accuracy, as the parameters are tuned to maintain fidelity to the original design behavior.
3Measurement precision
If constraint-based uncorrelated equivalence checking is applied, then trace-containment can be identified, but the process requires multiple iterations of obtaining candidate input sets and imposing constraints
Solution Approach 1:
The algorithm incorporates feedback mechanisms where results from previous equivalence checking iterations inform subsequent iterations. Mismatches identified in earlier passes generate constraints that are applied in later passes, and the process continues with refined candidate input sets based on previous findings. This feedback loop improves trace-containment detection accuracy while reducing redundant computations, thereby mitigating the time loss from multiple iterations.
Data Source
AI summary
Methods and systems are provided for producing more efficient digital circuitry designs by identifying trace-containment for a sequential circuitry design netlist through the use of constraint-based uncorrelated equivalence checking. A set of candidate input netlist sets n1 and n2 is first uncorrelated and then submitted for equivalence checking. Mismatches discovered during the equivalence checking are avoided by imposing constraint to the input set until discovering an equivalency relationship between the input sets n1 and n2.