Constraint-Based PAD Ring Layout for Chip ESD Capability
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Solution Overview
Problem
Existing automatic PAD ring layout methods in chip design fail to optimize electrostatic discharge (ESD) capability, necessitating manual adjustments by experienced designers, and thus cannot meet the requirements of chip designers effectively.
Innovation Solution
An automatic PAD ring layout method that determines PAD ring positions, Signal PADs, and power lead cells based on design data, area constraints, and technology library information, performing first and second automatic layouts to optimize ESD capability by inserting cells with maximum ESD capability and filler cells in residual gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If completely random layout under constraint conditions is used, then layout generation is simple and fast, but the generated layout cannot meet ESD capability requirements
Solution Approach 1:
The patent changes the layout parameters from completely random to systematically optimized positions. It calculates and determines specific position information for PAD ring boundaries and lead cells based on ESD capability requirements, transforming the layout from random placement to parameter-optimized placement that ensures proper ESD protection while maintaining automation.
Solution Approach 2:
The patent performs preliminary determination of PAD ring position information and lead cell distribution before actual layout generation. It pre-calculates the position coordinates and width information of PAD ring boundaries, and pre-determines the types and quantities of lead cells needed, ensuring that the subsequent automated layout process generates configurations that meet ESD requirements from the start.
2Reliability
If manual layout method is used, then ESD capability requirements can be met, but design time and complexity increase
Solution Approach 1:
The patent enables the layout system to determine and optimize its own configuration automatically. The automated system calculates PAD ring positions, determines lead cell types and quantities, and generates the complete layout without requiring manual intervention, making the system self-sufficient in meeting ESD capability requirements while maintaining design automation.
Solution Approach 2:
The patent incorporates constraint information and design requirements as feedback inputs that guide the automated layout generation. The system uses area constraint information, package constraint information, and core position information to continuously adjust and optimize the PAD ring and lead cell configuration, ensuring ESD capability is met while maintaining automation.
3Reliability
If manual adjustment is required, then layout meets design requirements, but automation level decreases
Solution Approach 1:
The patent creates a universal automated layout system that handles multiple functions: determining PAD ring positions, calculating boundary coordinates, determining lead cell types and quantities, and generating the complete layout. This multi-functional automated system replaces the need for manual adjustments while ensuring design requirements are met through systematic calculation and optimization.
Solution Approach 2:
The patent replaces the mechanical manual adjustment process with an automated computational system. Instead of manual layout adjustment, the system uses algorithmic calculation to determine optimal positions and configurations based on constraint information, substituting human manual operations with automated computational methods that maintain both automation and design requirement compliance.
Data Source
AI summary
An automatic layout method for a pad ring used for optimizing the electrostatic discharge capability of a chip, comprising: determining, on the basis of information of a selected process library and of package constraint information, the types and number of signal lead modules of a chip, and combined with designed total power consumption data, determining the types of power lead modules and a basic required number corresponding to each type of power lead modules; producing, on the basis of the types and the numbers of the signal lead cells and of that of the power supply lead modules and of the package constraint information, groups of lead modules to be laid out respectively for four boundaries; executing a first automatic layout with respect to each boundary; and executing a second automatic layout on the basis of the size of a remaining gap when the first automatic layout is executed.