System Constraints-Aware Scheduler for Heterogeneous Cores

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Solution Overview

Problem

The increased integration of digital processors in devices leads to excessive power consumption and dissipation, limiting the functionality of portable devices due to the limitations of their power supplies.

Innovation Solution

A system constraints-aware scheduler for heterogeneous computing architecture that dynamically allocates tasks between 'big' and 'little' cores based on real-time performance constraints such as temperature and battery level, using a hint generator to bias task scheduling and optimize system performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If processing intensive tasks are scheduled on bigger cores with higher speeds, then system performance is improved, but power consumption increases

Engineering Contradiction:
Improvesystem performanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The scheduler dynamically adapts task allocation strategies based on real-time system constraints including temperature, battery level, and performance requirements. The system transitions between different scheduling modes (performance-oriented, power-efficient, thermal-aware) to optimize the balance between productivity and energy consumption under varying operating conditions

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes scheduling parameters and task allocation decisions based on monitored system state parameters such as temperature thresholds, battery charge levels, and performance constraint parameters. This allows the system to adjust its energy consumption profile while maintaining acceptable performance levels

Inventive Principle:
Principle #35Parameter changes

2Productivity

If more tasks are scheduled on higher performing cores, then processing capability is improved, but temperature increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidsystem temperature
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The system continuously monitors temperature, battery level, and performance metrics, using this feedback to dynamically adjust task scheduling decisions. When temperature exceeds thresholds or battery level decreases, the scheduler modifies task allocation to reduce thermal load while maintaining performance within acceptable bounds

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The scheduling system dynamically responds to changing thermal conditions by adjusting task allocation in real-time, transitioning between performance-maximizing and thermal-managing modes based on current system state

Inventive Principle:
Principle #15Dynamics

3Device complexity

If traditional scheduling methods are used, then system simplicity is maintained, but adaptability to varying system constraints is reduced

Engineering Contradiction:
Improvescheduling system complexityVSAvoidadaptability to system constraints
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The scheduler is designed to handle multiple types of system constraints (thermal, power, performance) and different scheduling scenarios within a single unified framework, making the system adaptable to varying conditions without requiring separate specialized schedulers for each constraint type

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically adjusts its behavior based on monitored constraints, enabling adaptability to varying operating conditions while maintaining a relatively simple underlying scheduling architecture

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9612879B2System constraints-aware scheduler for heterogeneous computing architecture
Publication Date: 2017.04.04 TEXAS INSTRUMENTS INC
  • US9612879B2 patent drawing
  • US9612879B2 patent drawing
  • US9612879B2 patent drawing

AI summary

Processors, systems, and methods are arranged to schedule tasks on heterogeneous processor cores. For example, a scheduler is arranged to perform a heuristics based function for allocating operating system tasks to the processor cores. The system includes a hint generator providing a system constraints-aware function that biases the scheduler to select a processor core depending on the change in one or more performance constraint parameters.