Constricted Via Structure for Phase Change Memory Reset Current Reduction
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Solution Overview
Problem
Phase change memory devices face limitations in reducing the magnitude of the reset current required for transitioning from a crystalline to an amorphous state, as the current depends on the volume of phase change material, which is constrained by standard integrated circuit manufacturing processes, leading to challenges in achieving sublithographic dimensions with uniformity and reliability for high-density memory devices.
Innovation Solution
The development of memory cells with a constricted via structure that concentrates energy, allowing for a smaller active region with a width less than the minimum feature size of the manufacturing process, reducing the current needed for reset operations and improving uniformity by independent control of variations in the constricted part of the via.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If standard integrated circuit manufacturing processes are used, then manufacturing reliability is maintained, but the minimum feature size cannot be reduced below lithographic limits
Solution Approach 1:
The via structure is segmented into two distinct parts: a first part with a first cross-sectional area and a second part with a second cross-sectional area. This segmentation allows the constricted first part to achieve sub-lithographic dimensions while the enlarged second part remains manufacturable with standard lithographic processes, thus resolving the contradiction between feature size reduction and manufacturing ease.
Solution Approach 2:
The invention transitions from a uniform via structure to a multi-dimensional via structure with varying cross-sectional areas along its length. By utilizing the vertical dimension to create the constricted first part and enlarged second part, the design achieves sub-lithographic effective area without requiring sub-lithographic lithographic patterning, thereby maintaining manufacturing ease while improving precision.
2Use of energy by moving object
If the volume of phase change material is reduced, then reset current magnitude is reduced, but uniformity and reliability of memory cell operation deteriorate
Solution Approach 1:
The via structure implements local quality by creating a constricted first part with reduced cross-sectional area where the phase change material is located. This local reduction in volume decreases the reset current magnitude, while the enlarged second part provides sufficient material volume to maintain uniformity and reliability across memory cells. The differential sizing allows simultaneous optimization of both energy consumption and operational reliability.
3Use of energy by moving object
If the active region size is reduced below minimum feature size, then reset current is reduced, but manufacturing uniformity deteriorates
Solution Approach 1:
The via is segmented into a constricted first part and an enlarged second part, where only the first part contains the active phase change material. This segmentation allows the first part to have sub-lithographic dimensions for low reset current, while the second part maintains larger, more uniformly manufacturable dimensions, thus resolving the contradiction between reduced reset current and manufacturing precision.
Solution Approach 2:
The enlarged second part of the via acts as an intermediary structure that connects the constricted first part to the electrodes. It provides mechanical support and electrical connection while maintaining manufacturable dimensions, allowing the active first part to achieve sub-lithographic size without compromising overall manufacturing uniformity or reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the reduction of the reset current magnitude and enhances the uniformity of memory cell operation, enabling the creation of high-density memory devices with reliable and repeatable manufacturing techniques.
Implementation Method 1
the constricted region causing energy passing through the memory element to be concentrated in the constricted region
Implementation Method 2
Phase change based memory materials are widely used in read-write optical disks. These materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase.
Implementation Method 3
Current heats the material and causes transitions between the states
Data Source
AI summary
A memory cell includes a memory cell layer with a first dielectric layer over a bottom electrode layer, a second dielectric layer over the first dielectric layer, and a top electrode over the second dielectric layer. The dielectric layers define a via having a first part bounded by the first electrode layer and the bottom electrode and a second part bounded by the second dielectric layer and the top electrode. A memory element is within the via and is in electrical contact with the top and bottom electrodes. The first and second parts of the via may comprise a constricted, energy-concentrating region and an enlarged region respectively. The constricted region may have a width smaller than the minimum feature size of the process used to form the enlarged region of the via. A method for manufacturing a memory cell is also disclosed.