Contact Adjustment Layers for Void-Free Low-Capacitance Interconnects
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Solution Overview
Problem
Challenges arise during the scaling-down process of semiconductor devices, affecting quality, yield, performance, and reliability, with issues related to void formation in contact structures and increased parasitic capacitance.
Innovation Solution
A semiconductor device design featuring adjustment layers on the sidewalls of contacts, a contact barrier layer, and a porous insulating layer to prevent voids and reduce parasitic capacitance, with specific materials and fabrication methods to ensure precise construction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact structures are used during scaling-down, then manufacturing simplicity is maintained, but void formation occurs and yield decreases
Solution Approach 1:
The contact structure is segmented into multiple functional layers: a contact barrier layer at the bottom, adjustment layers on the sidewalls with varying thicknesses, and a contact fill material. This segmentation allows each layer to perform its specific function independently, preventing void formation while maintaining manufacturing feasibility
Solution Approach 2:
The contact barrier layer and adjustment layers are formed conformally on the sidewalls before contact fill material deposition. This preliminary action creates a pre-structured template that guides the contact fill material deposition, ensuring complete filling without voids and improving yield
2Reliability
If conventional insulating layers are used, then manufacturing simplicity is maintained, but parasitic capacitance increases and performance deteriorates
Solution Approach 1:
The first insulating layer is formed as a porous structure with controlled void spaces, reducing the dielectric constant and thereby decreasing parasitic capacitance between interconnection structures. This improves device performance while the porous structure is integrated into the existing manufacturing process
Solution Approach 2:
The insulating layer structure combines multiple materials with different properties: a first insulating layer with porous low-k material for capacitance reduction, and a second insulating layer with different dielectric properties. This composite structure optimizes electrical performance while managing manufacturing complexity
Data Source
AI summary
The present application discloses a semiconductor device with adjustment layers and a method for fabricating the semiconductor device with the adjustment layers. The semiconductor device includes a substrate, an interconnection structure positioned on the substrate, a contact positioned penetrating the interconnection structure, two adjustment layers positioned on sidewalls of the contact, a contact barrier layer positioned between the interconnection structure and the contact and between the substrate and the contact, wherein the two adjustment layers are positioned between the contact and the contact barrier layer. A bottom segment of the contact barrier layer is positioned between the substrate and the contact, and bottom most points of the two adjustment layers contact the bottom portion of the contact barrier layer.