Contact Adjustment Layers for Void-Free Semiconductor Contacts
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Solution Overview
Problem
The challenge in scaling down semiconductor devices is to improve quality, yield, performance, and reliability while reducing complexity, particularly in forming contacts without voids and minimizing parasitic capacitance.
Innovation Solution
The semiconductor device incorporates a substrate with an interconnection structure, a contact penetrating the structure, and adjustment layers on the contact's sidewalls. The adjustment layers are formed of metal oxide, metal nitride, or metal carbide and have a thickness that gradually decreases toward the substrate, improving contact formation without voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact formation methods are used in scaled-down semiconductor devices, then manufacturing process remains simple, but voids form in contacts reducing yield and reliability
Solution Approach 1:
The contact structure is segmented into multiple functional layers: a contact barrier layer at the bottom and adjustment layers on the sidewalls. This segmentation allows each layer to perform its specific function - the barrier layer prevents diffusion and the adjustment layers control deposition and prevent voids - thereby improving contact formation quality without requiring overly complex processes
Solution Approach 2:
The contact barrier layer and adjustment layers are formed conformally on the contact sidewalls before the contact material is deposited. This preliminary action prepares the surface to control deposition rates and prevent void formation during subsequent contact material filling, ensuring void-free contacts while maintaining a relatively simple overall process
2Reliability
If solid insulating layers are used in interconnection structures, then structural integrity is maintained, but parasitic capacitance increases reducing device performance
Solution Approach 1:
The first insulating layer is formed with a porous structure containing nanoscale voids. This porous configuration reduces the dielectric constant of the material, thereby reducing parasitic capacitance between interconnection structures and improving device performance. The porous structure maintains sufficient mechanical integrity while achieving the desired electrical performance
Solution Approach 2:
The dielectric constant parameter of the insulating layer is changed by introducing porosity. By controlling the pore size, distribution, and density in the first insulating layer, the effective dielectric constant is reduced from typical values (e.g., SiO2 at 3.9) to lower values, directly reducing parasitic capacitance while maintaining the layer's structural function
Data Source
AI summary
The present application discloses a semiconductor device with adjustment layers and a method for fabricating the semiconductor device with the adjustment layers. The semiconductor device includes a substrate, an interconnection structure positioned on the substrate, a contact positioned penetrating the interconnection structure, two adjustment layers positioned on sidewalls of the contact, a contact barrier layer positioned between the interconnection structure and the contact and between the substrate and the contact, wherein the two adjustment layers are positioned between the contact and the contact barrier layer. A bottom segment of the contact barrier layer is positioned between the substrate and the contact, and bottom most points of the two adjustment layers contact the bottom portion of the contact barrier layer.