Semiconductor Contact Structure With Air Gap for Overlay Precision
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Solution Overview
Problem
The aggressive scaling of semiconductor IC dimensions leads to densely spaced gate structures and source/drain contacts, posing challenges in forming accurate gate contacts and source/drain contact vias due to high overlay precision requirements, which existing techniques have not adequately addressed, resulting in issues like electrical shorts and increased parasitic capacitance.
Innovation Solution
The method involves forming a contact structure to the source/drain region by providing a reduced thickness spacer structure to create sufficient space between adjacent gate structures, allowing for insulation through an air gap, which reduces parasitic capacitance while maintaining control over the contact structure profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If aggressive scaling of IC dimensions is performed, then production efficiency is improved and costs are lowered, but overlay precision requirements increase leading to electrical shorts and leakage
Solution Approach 1:
A spacer structure is introduced as an intermediary element between the gate structure and source/drain contact. This spacer acts as a mediator that defines the lateral extent of the contact, eliminating the need for high-precision overlay between separate contact and gate patterning steps. The spacer's outer perimeter determines the contact opening location, serving as a self-aligned reference that prevents misalignment issues.
Solution Approach 2:
The spacer structure is formed in advance before the contact opening is created. By pre-forming the spacer with the desired lateral dimensions and position, the subsequent contact opening process can be performed with relaxed precision requirements, as the spacer already establishes the correct lateral boundaries for the contact.
2Quantity of substance
If densely spaced gate structures are used, then device integration is improved, but parasitic capacitance increases
Solution Approach 1:
The spacer material is selectively removed (etched) to form the contact opening, extracting the dielectric material that would otherwise contribute to parasitic capacitance between the gate and source/drain regions. This creates a void or reduced-dielectric region that minimizes capacitive coupling while maintaining the dense spacing of gate structures for high integration.
3Ease of manufacture
If conventional contact formation techniques are used, then manufacturing simplicity is maintained, but contact alignment precision deteriorates
Solution Approach 1:
The spacer structure serves a dual function: it acts as both a structural element defining the contact lateral boundaries and as a self-aligned mask for the contact opening process. The contact opening is formed using the spacer's outer perimeter as the alignment reference, making the process self-serviceing and eliminating the need for separate alignment operations between contact and gate patterning.
Data Source
AI summary
Methods and devices including an air gap adjacent a contact element extending to a source/drain feature of a device are described. Some embodiments of the method include depositing a dummy layer, which is subsequently removed to form the air gap. The dummy layer and subsequent air gap may be formed after a SAC dielectric layer such as silicon nitride is formed over an adjacent metal gate structure.


