Insulating Contact Cap Structure to Prevent FinFET Via Bridging
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Solution Overview
Problem
Existing FinFET manufacturing processes face challenges in forming reliable via and contact structures as device scaling-down continues, particularly in preventing bridging between source/drain contact structures and via structures over the gate stack.
Innovation Solution
The implementation of a semiconductor device structure that includes a first insulating capping feature over a gate stack and a second insulating capping feature with a different material over the source/drain contact structure, which serves as a hard mask during etching, preventing bridging and providing etching selectivity, thus eliminating the need for an etch stop layer and reducing via structure height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional FinFET manufacturing processes are used, then existing process simplicity is maintained, but reliable via and contact structures cannot be formed at smaller sizes and bridging between contact structures and via structures occurs
Solution Approach 1:
The process is segmented into distinct etching stages: first etching the insulating layer to form initial openings, then etching the insulating capping features to form via structures. This segmentation allows precise control over via opening definition and prevents bridging between contact structures and via structures, resolving the contradiction between manufacturing precision and process complexity.
Solution Approach 2:
Insulating capping features are formed over the gate stack before via etching. These capping features serve as preliminary protective structures that define the via opening boundaries and prevent unwanted etching into contact structures, enabling reliable via formation at smaller sizes without increasing overall process complexity.
2Reliability
If via structure height is reduced, then via structure resistance decreases, but etching control and prevention of bridging become more difficult
Solution Approach 1:
The insulating capping features act as intermediary structures between the insulating layer and the contact structures. During via etching, these capping features serve as etch masks that precisely define via opening locations and prevent etching from bridging into contact structures, enabling both reduced via height and improved etching control.
Solution Approach 2:
The insulating capping features provide localized protection and definition only where via openings are required, rather than requiring comprehensive protective structures throughout the entire device. This localized approach enables precise via formation with reduced height while maintaining etching control, improving via structure performance without sacrificing manufacturing precision.
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes forming a gate structure over a semiconductor substrate. The gate structure includes a gate electrode layer, a gate dielectric layer covering two opposite sidewalls and a bottom of the gate electrode layer, and two gate spacers correspondingly covering portions of gate dielectric layer that covers the two opposite sidewalls of the gate electrode layer. The method also includes forming a contact structure adjacent to one of the two gate spacers, successively recessing the contact structure and the one of the two gate spacers to form a recess that exposes the contact structure and the one of the two gate spacers, and forming a first insulating capping feature in the recess to cover and a top of the contact structure.