Insulating Contact Cap Structure for FinFET Via Isolation
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Solution Overview
Problem
Existing FinFET manufacturing processes face challenges in forming reliable via and contact structures as device scaling-down continues, particularly in preventing bridging between source/drain contact structures and via structures, and achieving adequate etching selectivity.
Innovation Solution
The implementation of a semiconductor device structure with a first insulating capping feature over a gate stack and a second insulating capping feature with a different material over the source/drain contact structure, which serves as a hard mask during etching and provides etching selectivity, eliminating the need for an etch stop layer and reducing via structure height, thereby improving etching capability and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing FinFET manufacturing processes are used, then general fabrication is achieved, but reliable via and contact structure formation becomes difficult as device scaling continues
Solution Approach 1:
The patent divides the capping structure into two distinct segments: a first insulating capping material and a second insulating capping material with different etching selectivity. This segmentation allows each layer to serve specific functions during etching processes, enabling precise control over via and contact hole formation while maintaining reliability during device scaling.
Solution Approach 2:
The patent applies different materials with specific local properties at different locations in the capping structure. The first insulating capping material provides baseline insulation, while the second insulating capping material provides enhanced etching selectivity in specific regions, creating local quality variations that improve manufacturing precision for via and contact structures.
2Device complexity
If conventional single-layer capping structures are used, then process simplicity is maintained, but bridging between source/drain contact structures and via structures cannot be prevented
Solution Approach 1:
By segmenting the capping structure into two insulating material layers, the patent creates distinct functional zones that prevent bridging between source/drain contact structures and via structures. The first layer provides fundamental isolation, while the second layer with different etching selectivity provides an additional protective barrier, thereby maintaining reliability without excessive complexity.
Solution Approach 2:
The two-layer insulating capping structure acts as an intermediary barrier between the source/drain contact structures and the via structures. This intermediate structure prevents direct contact and potential bridging, while still allowing the necessary electrical connections to be formed through controlled etching processes.
3Manufacturing precision
If etch stop layers are used to achieve etching selectivity, then via opening definition is improved, but process complexity and via structure height increase
Solution Approach 1:
The patent makes the insulating capping structure multi-functional by selecting the second insulating capping material to provide both the capping function and the etching selectivity function. This eliminates the need for a separate etch stop layer, as the second insulating material layer serves dual purposes: protecting underlying structures and enabling precise via opening definition through its different etching characteristics.
Solution Approach 2:
The patent merges the functions of the insulating capping layer and the etch stop layer into a single integrated structure. The second insulating capping material layer combines the protective capping function with the etching selectivity function, thereby reducing process complexity and via structure height while maintaining precise via opening definition.
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A gate dielectric layer covers opposite sidewalls and a bottom of the conductive gate stack. A first gate spacer layer and a second gate spacer layer respectively cover portions of the gate dielectric layer corresponding to the opposite sidewalls of the conductive gate stack. A source/drain contact structure is separated from the conductive gate stack by the gate dielectric layer and the first gate spacer layer. A first insulating capping feature covers the conductive gate stack and is separated from the second gate spacer layer by the gate dielectric layer, and a second insulating capping feature covers the source/drain contact structure. An upper surface of the second insulating capping feature is substantially level with an upper surface of the first insulating capping feature.