Contact Electrodes with Segmented Dielectric Overlap for TFTs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Thin-film transistors (TFTs) in back-gated architectures face significant parasitic capacitance issues, which worsen with scaling, leading to increased access resistances and performance loss, and existing techniques to reduce parasitic capacitance often compromise on device speed and scalability.
Innovation Solution
The implementation of a contact electrode with multiple portions over one or more dielectric layers, where the first portion overlaps only with the first gate dielectric layer, and the second portion overlaps with both the first and second dielectric layers, effectively reducing overlap capacitances without increasing access resistances, thereby enhancing device speed and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the contact electrode is extended to overlap with the gate electrode to reduce access resistance, then the access resistance decreases, but the parasitic capacitance increases
Solution Approach 1:
The contact electrode is divided into multiple portions: a first portion that overlaps with the gate electrode to reduce access resistance, and a second portion that is separated from the gate electrode by a dielectric layer to minimize parasitic capacitance. This segmentation allows the electrode to simultaneously achieve low resistance and low capacitance by distributing its function across different spatial zones.
2Productivity
If the TFT is scaled down to improve integration density, then the integration density increases, but the parasitic capacitance effects worsen
Solution Approach 1:
The patent introduces a vertical dimension by stacking dielectric layers between the contact electrode and gate electrode. This vertical separation allows the contact electrode to maintain functional overlap for low resistance while physically distancing itself to reduce capacitance, a solution that becomes increasingly important as devices are scaled down for higher integration density.
3Object-generated harmful factors
If the overlap area between contact electrode and gate electrode is reduced to decrease parasitic capacitance, then the parasitic capacitance decreases, but the access resistance increases
Solution Approach 1:
Different portions of the contact electrode are assigned different functional qualities: the first portion has extensive overlap with the gate electrode to minimize access resistance, while the second portion is separated by dielectric layers to minimize parasitic capacitance. This local differentiation of electrode properties allows simultaneous optimization of both resistance and capacitance characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a faster and more scalable TFT in back-gated architectures by minimizing parasitic capacitance while maintaining low access resistances, thus addressing the limitations of existing TFT designs.
Implementation Method 1
a first gate dielectric layer including a first gate dielectric material above the gate electrode; a second dielectric layer above a portion of the first gate dielectric layer
Data Source
AI summary
Embodiments herein describe techniques for a transistor above the substrate. The transistor includes a first gate dielectric layer with a first gate dielectric material above a gate electrode, and a second dielectric layer with a second dielectric material above a portion of the first gate dielectric layer. A first portion of a channel layer overlaps with only the first gate dielectric layer, while a second portion of the channel layer overlaps with the first gate dielectric layer and the second dielectric layer. A first portion of a contact electrode overlaps with the first portion of the channel layer, and overlaps with only the first gate dielectric layer, while a second portion of the contact electrode overlaps with the second portion of the channel layer, and overlaps with the first gate dielectric layer and the second dielectric layer. Other embodiments may be described and/or claimed.