Contact Etch Stop Layer Layout for Lower GAA Parasitic Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing advanced ICs due to increased complexity and power dissipation issues as devices scale down, requiring innovative solutions for efficient processing and reduced parasitic resistance.
Innovation Solution
The use of a contact etch stop layer with varying thickness and composition to modulate contact opening depths and areas for source/drain epitaxial structures, optimizing channel stress and parasitic resistance in GAA transistor structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but power dissipation increases
Solution Approach 1:
The patent changes the physical parameters of the contact etch stop layer, specifically varying its thickness (first thickness over first source/drain epitaxial structure, second thickness over second source/drain epitaxial structure) and material composition to modulate contact opening depths and areas, thereby optimizing device performance while maintaining scaled dimensions
Solution Approach 2:
The patent applies different thicknesses and compositions of the contact etch stop layer at different locations (first portion over first source/drain epitaxial structure, second portion over second source/drain epitaxial structure) to create local variations that optimize channel stress and parasitic resistance for each device region
2Reliability
If contact opening depth is increased to reduce parasitic resistance, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent uses parameter changes in the contact etch stop layer thickness and composition to control etch depth, allowing deeper contact openings in regions where lower parasitic resistance is needed without requiring additional etch steps or masks
Solution Approach 2:
The contact etch stop layer is prepared in advance with predetermined thickness variations before the contact etching process, so that the etch depth is pre-determined by the layer structure rather than requiring complex real-time control or multiple processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by lowering channel resistance and parasitic resistance, allowing for deeper contact areas without additional masks, and integrates with epitaxial growth processes for optimized semiconductor device manufacturing.
Implementation Method 1
integrates with epitaxial growth processes for optimized semiconductor device manufacturing
Data Source
AI summary
A semiconductor device includes a first channel region, a second channel region, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a contact etch stop layer, and an interlayer dielectric layer. The gate structure is across the first channel region and the second channel region. The first source/drain epitaxial structure is on a side of the first channel region. The second source/drain epitaxial structure is on a side of the second channel region. The contact etch stop layer surrounds the first source/drain epitaxial structure and the second source/drain epitaxial structure. A first portion of the contact etch stop layer over the first source/drain epitaxial structure is thicker than a second portion of the contact etch stop layer over the second source/drain epitaxial structure. The interlayer dielectric layer is over the contact etch stop layer.