Contact Etch Stop Layer Protects Metal Gate During Fabrication
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Solution Overview
Problem
In integrated circuit fabrication, particularly in CMOS technology, there is a challenge in forming metal gate structures due to low etch selectivity during contact etching, which can lead to recess formation and damage to the metal gate, exacerbated by shrinking technology nodes and reduced gate lengths.
Innovation Solution
The implementation of a method involving the use of contact etch stop layers, specifically silicon nitride or carbon-doped silicon nitride, deposited in multiple stages to protect the metal gate structure during etching, including a first contact etch stop layer and a second layer with varying thicknesses to enhance selectivity and prevent recess formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If contact etching is performed to form contacts in CMOS fabrication, then contact holes can be formed, but recess formation and damage to the metal gate structure occurs due to low etch selectivity
Solution Approach 1:
A contact etch stop layer is introduced as an intermediary material between the metal gate structure and the contact etch process. This layer has high etch selectivity, allowing the etch to stop precisely at the metal gate interface without damaging it, thus preventing recess formation while enabling contact hole formation.
Solution Approach 2:
The contact etch stop layer is deposited in advance before the contact etching process. This preliminary action prepares the structure with a protective barrier that prevents damage during the subsequent etching step, ensuring metal gate integrity before the actual contact formation occurs.
2Productivity
If technology nodes are shrunk to improve device density, then integration capacity increases, but etch selectivity between metal gate and contact etch stop layer decreases
Solution Approach 1:
The material composition and thickness parameters of the contact etch stop layer are optimized for scaled technology nodes. By adjusting these parameters, high etch selectivity is maintained even as feature sizes decrease, enabling precise contact formation without metal gate damage in advanced technology nodes.
Solution Approach 2:
A multi-layer composite structure is used, combining the metal gate structure with the contact etch stop layer having distinct material properties. This composite approach allows tailored etch selectivity through material composition optimization, maintaining manufacturing precision despite technology node scaling.
3Manufacturing precision
If gate oxide thickness is reduced to maintain performance with decreased gate length, then transistor performance is maintained, but gate leakage increases
Solution Approach 1:
A composite gate dielectric structure is employed, combining thin gate oxide with high-k dielectric material. The thin oxide layer (e.g., 1-2 nm) provides excellent interface quality and mobility, while the high-k layer adds thickness to reduce gate leakage, achieving both performance and low leakage in scaled devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents unwanted etching of the metal gate structure, maintaining device performance by reducing recess formation and enhancing the protection of the metal gate structure during contact etching, thereby improving the reliability of the fabrication process.
Implementation Method 1
low etch selectivity between the metal gate structure and a contact etch stop layer
Implementation Method 2
depositing a contact etch stop layer over the first interlayer dielectric layer and the top surface of the gate structure
Data Source
AI summary
A method for fabricating a field-effect transistor includes forming a spacer adjacent to sidewalls of a gate structure. The method further includes forming silicide regions in a substrate adjacent to the spacer. The method further includes depositing a first interlayer dielectric layer over the substrate. The method further includes exposing a top surface of the gate structure. The method further includes depositing a contact etch stop layer over the first interlayer dielectric layer and the top surface of the gate structure. The method further includes patterning the contact etch stop layer to remove a portion of the contact etch stop layer over the silicide regions, wherein the contact etch stop layer over the gate structure is maintained.