Contact Field Plate Structure for High-Breakdown LDMOS
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Solution Overview
Problem
Existing LDMOS devices face challenges in achieving high breakdown voltage while minimizing specific on-resistance (Rds (on)) to reduce conduction loss, which is crucial for quick-charging devices with high current capacity.
Innovation Solution
The semiconductor device incorporates a contact field plate (CFP) with multiple poly straps and a reduced surface field oxide (ROX) layer, which prevents over-etching, reduces gate-induced drain leakage (GIDL), and decreases manufacturing costs by eliminating the need for a composite etch stop layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If conventional LDMOS device structure is used, then manufacturing process is simpler, but breakdown voltage is insufficient and on-resistance is high
Solution Approach 1:
The patent implements a nested structure where the contact field plate is positioned within the drift region, surrounded by the inter-level dielectric layer, which is in turn surrounded by the passivation layer. This nested arrangement allows multiple functional layers to be integrated in a compact configuration, enhancing breakdown voltage without proportionally increasing device footprint or manufacturing complexity.
Solution Approach 2:
The patent transitions from a planar device structure to a three-dimensional structure by adding the contact field plate extending vertically from the drift region through the inter-level dielectric layer to the passivation layer. This vertical dimensionality increase allows for enhanced electric field control and higher breakdown voltage while maintaining a compact planar footprint.
2Loss of energy
If higher breakdown voltage is achieved through conventional means, then on-resistance increases, but lower on-resistance is desired for quick-charging devices
Solution Approach 1:
The patent applies local quality by creating a non-uniform doping profile in the drift region with the contact field plate having a specific doping concentration that differs from other regions. This localized doping optimization allows the drift region to simultaneously support high breakdown voltage through appropriate doping in the bulk while maintaining low on-resistance through optimized doping near the contact field plate, thereby reducing conduction loss without sacrificing voltage handling capability.
3Manufacturing precision
If composite etch stop layer is used to prevent over-etching, then manufacturing precision improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements self-service by designing the contact field plate structure where the inter-level dielectric layer and passivation layer inherently provide etch stopping capability during contact hole formation. The natural layering and material properties of these dielectric layers serve as built-in etch stops, eliminating the need for additional dedicated etch stop layers and simplifying the overall device structure while maintaining manufacturing precision.
4Area of stationary object
If more components are integrated on single die, then board footprint is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies universality by designing the contact field plate structure to serve multiple functions simultaneously: it acts as an electrical contact, provides field plate functionality for voltage control, serves as an etch stop, and contributes to overall device isolation. This multi-functionality reduces the need for separate dedicated structures, allowing higher component integration on a single die without proportionally increasing manufacturing precision requirements.
Data Source
AI summary
A method for manufacturing a semiconductor device is provided. A gate oxide layer is formed over an N-type well region and a P-type well region. The gate oxide layer comprises an input/output (I/O) oxide layer portion and a reduced surface field oxide (ROX) layer portion. A poly gate is formed on the I/O oxide layer portion. The poly gate extends along an interface between the N-type well region and the P-type well region. At least one poly strap is formed on the ROX layer portion. A resist protect oxide (RPO) layer is formed to completely cover the poly strap and partially cover the poly gate. An inter-level dielectric (ILD) layer is formed over the RPO layer. A connecting feature is formed to penetrate the ILD layer and the RPO layer to contact the poly strap.