Contact First Replacement Metal Gate for Sub-32nm Devices
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Solution Overview
Problem
In advanced semiconductor technologies, particularly for sub-32 nanometer devices, the tight gate-to-gate spacing and design requirements pose challenges in placing contacts between gates due to small contact sizes, leading to issues like high contact resistance, leakage, and misalignment, which are exacerbated by multiple patterning processes such as LELELE, resulting in underetching and overetching problems.
Innovation Solution
The method involves forming sacrificial gates, growing epitaxial layers, depositing and recessing contact materials, and removing masking materials to create exposed contact areas, followed by replacing sacrificial gates with metal gates and forming caps, ensuring accurate contact formation and reduced processing difficulties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple patterning processes (LELELE) are used to place contacts between gates, then contact placement is achieved, but manufacturing complexity increases and alignment precision deteriorates
Solution Approach 1:
The contact opening is formed before the gate structure is fully defined. The method performs contact first etching to create openings in the interlayer dielectric, then forms the gate structures around these pre-existing openings. This preliminary action eliminates the need for subsequent contact openings through multiple patterning processes, reducing manufacturing complexity from six to eight masks down to three masks in a triple exposure process.
2Ease of manufacture
If multiple patterning processes (LELELE) are used to place contacts between gates, then contact placement is achieved, but alignment precision between gate and contact deteriorates
Solution Approach 1:
By forming contact openings first before gate patterning, the alignment reference is established early in the process. The gate structures are then self-aligned to these pre-formed contacts, eliminating cumulative overlay errors that would accumulate through six to eight sequential masking steps. This reverses the conventional sequence to achieve superior alignment precision.
Solution Approach 2:
The conventional sequence is inverted: instead of forming gates first then opening contacts through multiple patterning, the method forms contacts first and then builds gates around them. This inversion transforms a complex multi-step contact opening process into a simpler self-aligned process, dramatically improving both ease of manufacture and alignment precision.
3Ease of manufacture
If SAC processes with triple exposure are used, then contact formation is achieved, but etch variability increases leading to underetching and overetching
Solution Approach 1:
Contact openings are formed as the first patterning step before any gate structures exist. This preliminary contact formation establishes a reference framework that guides subsequent gate patterning. The etch process for contacts is performed when the pattern density is uniform and controlled, avoiding the etch variability that would occur in subsequent steps with varying pattern densities.
4Ease of manufacture
If contact size is reduced to fit tight gate-to-gate spacing, then contact placement between gates is achieved, but contact resistance increases
Solution Approach 1:
Contact openings are formed first with optimal dimensions before gate structures are built around them. This allows contacts to be sized for low resistance without being constrained by subsequent gate placement requirements. The preliminary contact formation ensures adequate contact area for reliable electrical connection while maintaining compatibility with tight gate-to-gate spacing through the self-aligned approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures improved contact area reactions, reduced processing complexities, and enhanced resistance, addressing the limitations of conventional methods by providing more precise control over contact formation and reducing defects like hollow metal voids.
Implementation Method 1
growing epitaxial layers on one or more source-drain areas between the sacrificial gates by an epitaxial growth process
Data Source
AI summary
A technique relates to forming a semiconductor device. Sacrificial gates are formed on a channel region of a substrate. Epitaxial layers are grown on source-drain areas between the sacrificial gates. A contact liner and contact material are deposited. The liner and the contact material are removed from above the sacrificial gates. Contact areas are blocked with one or more masking materials and etched. The masking material is removed. The contact material is partially recessed and a nitride liner deposited. An oxide layer is deposited and the sacrificial gate is removed. A metal gate is formed on the channel region and recessed. Insulator material and metal gate material are recessed and a cap is formed over the gate.