Contact Gate Isolation Liner for GAA Leakage Spacing
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Solution Overview
Problem
The integration of gate-all-around (GAA) transistor features around silicon nanowires/nanosheets in semiconductor manufacturing is challenging, requiring improved processes to enhance gate control and mitigate short-channel effects while scaling down.
Innovation Solution
The method involves recessing the gate dielectric layer to expose the top gate electrode layer, reducing the dimension of the top portion of the final gate stack, and increasing the spacing between the contact plug and the final gate stack, thereby improving the reliability of the semiconductor device and facilitating the scaling down of the gate-to-gate pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate dielectric layer is recessed to expose the top gate electrode layer, then the spacing between the contact plug and the final gate stack is increased, improving reliability and reducing leakage risk, but the manufacturing process complexity increases
Solution Approach 1:
The gate dielectric layer is recessed in advance before contact plug formation, creating a stepped structure that pre-establishes the spacing between the contact plug and gate stack. This preliminary action prevents potential leakage paths and improves reliability before subsequent processing steps are performed.
Solution Approach 2:
The gate dielectric layer is segmented into different levels: a first portion remains at the original level while a second portion is recessed to expose the top gate electrode layer. This segmentation creates distinct functional zones that improve electrical isolation and reduce leakage risk between the contact plug and gate stack.
2Productivity
If the dimension of the top portion of the final gate stack is reduced, then the overlay window of the photolithography process is relaxed, facilitating scaling down of the gate-to-gate pitch, but the manufacturing precision requirements increase
Solution Approach 1:
The gate stack dimension is reduced in the vertical dimension by recessing the gate dielectric layer, rather than reducing horizontal dimensions. This dimensional change approach relaxes the overlay window requirements for photolithography while still achieving the goal of facilitating gate-to-gate pitch scaling.
Data Source
AI summary
Gate isolation processes (e.g., gate-to-source/drain contact isolation) are described herein. An exemplary contact gate isolation process may include recessing (e.g., by etching) sidewall portions of a high-k gate dielectric and gate spacers of a gate structure to form a contact gate isolation (CGI) opening that exposes sidewalls of a gate electrode of the gate structure, forming a gate isolation liner along the sidewalls of the gate electrode that partially fills the CGI opening, and forming a gate isolation layer over the gate isolation liner that fills a remainder of the CGI opening. A dielectric constant of the gate isolation liner is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer may be less than a dielectric constant of the gate isolation layer.