Anisotropic Doping of Semiconductor Contact Hole Sidewalls
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down transistor interconnect structures due to increased junction resistance, which degrades switching speed, and existing pre-clean processes can damage peripheral components, leading to short circuits.
Innovation Solution
An anisotropic doping process is applied to the sidewalls of contact holes in semiconductor devices to increase etch resistivity, allowing them to withstand pre-clean processes without damage, thereby preventing short circuits and maintaining structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a pre-clean process is performed to remove oxides and residues, then the junction resistance decreases, but the peripheral components and structures are damaged causing short circuits
Solution Approach 1:
The patent applies different properties to different parts of the contact hole structure. The sidewall receives anisotropic doping to create a protective layer with different etch resistance properties, while the bottom of the contact hole remains clean for good electrical contact. This local differentiation allows the pre-clean process to remove oxides from the contact area without damaging the peripheral spacer layer and gate electrode.
Solution Approach 2:
The anisotropic doping process is performed in advance before the pre-clean etching process. This preliminary action creates a protective layer on the sidewall that will withstand the subsequent etching process, preventing damage to peripheral components while still allowing oxide removal from the contact area.
2Reliability
If the contact hole sidewall is doped anisotropically, then the etch resistivity increases protecting against pre-clean damage, but the process complexity increases
Solution Approach 1:
The patent combines the anisotropic doping step with the existing contact hole formation process sequence. The doping is performed using the same mask and alignment infrastructure already in place for contact hole definition, merging the protective layer formation into the existing process flow rather than adding completely separate process equipment or alignment systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces etch rate and prevents damage during pre-clean processes, ensuring seamless integration with existing CMOS fabrication technologies and enhancing transistor performance by avoiding short circuits.
Implementation Method 1
doping an upper portion of the first sidewall
Data Source
AI summary
A method of making a semiconductor device includes forming a gate stack that include a gate electrode and a spacer layer extending along a sidewall of the gate electrode; forming a source/drain (S/D) feature that is adjacent to the gate stack; forming a dielectric layer over the gate stack and the S/D feature; forming a contact hole in the dielectric layer to expose the S/D feature, wherein the contact hole includes a first sidewall that is formed by the spacer layer and part of the dielectric layer; doping an upper portion of the first sidewall; and performing an etching process thereby cleaning oxides in the contact hole.